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RE: TMS320F280049C: General CLA questions

Other Parts Discussed in Thread: TMS320F280049C

Thanks Lori,

That resolved my issue but I just have some more relevant question i.e.
-- If I run CLA and main CPU then how can I make the work synchronously?
--In reference to above example, each time CLA_Task1 is called the main cpu executes a CLA_task1 ISR where the data is collected by the CPU_1. Is there any way to avoid ISR so that the main CPU can work without interrupts from CLA.
-- Are there any more ways to give data to the main CPU. for example, I make an array in CLA and just pass its address to main_CPU?
-- While I am using CLA, I am short of memory. I am using all 8 LS RAMs. Can I increase it further by including other memories?
-- I want to store the data using DMA. Is there any DMA example for this platform, using CLA?

Regards,

Bilal

  • Note: I split your new questions into a new thread.  This helps us track the questions and resolution.  In the future you can select "ask a related question" or "ask a new question" - this would be very helpful and will help TI track the question(s) and resolution.  Sometimes follow-on questions to a resolved thread are missed unfortunately.

    Bilal,

    I feel the following resources will be helpful to you.  You will find the first two on the product folder for the TMS320F280049C

    • The data manual for the F280049C: This has information regarding the memory blocks on the device, their location and how they can be accessed. 
    • The Technical Reference manual for F280049C: This has more detail on the CLA features on this device.
    • The CLA workshop https://training.ti.com/control-law-accelerator-cla-hands-workshop  This is for an older device, but still a very good introduction to the CLA.  One new, very useful, feature on F28004x is the ability to make task 8 a background interruptable task.

    Q: If I run CLA and main CPU then how can I make the work synchronously?

    A: The CLA tasks run when triggered.  The trigger can occur by the main CPU or by a peripheral.  For the list of peripherals refer to the technical reference manual for the specific device.

    In the example (cla_ex1_adc_fir) the CLA task 8 is triggered by the CPU and the trigger source for task 1 is the ADC.  Look in the code for the following lines:

        CLA_setTriggerSource(CLA_TASK_1, CLA_TRIGGER_ADCA1);
        CLA_setTriggerSource(CLA_TASK_8, CLA_TRIGGER_SOFTWARE);
        CLA_enableTasks(CLA1_BASE, (CLA_TASKFLAG_1 | CLA_TASKFLAG_8));
        CLA_enableIACK(CLA1_BASE);
        CLA_forceTasks(CLA1_BASE, CLA_TASKFLAG_8);

    Q: In reference to above example, each time CLA_Task1 is called the main cpu executes a CLA_task1 ISR where the data is collected by the CPU_1. Is there any way to avoid ISR so that the main CPU can work without interrupts from CLA. 

    A: Yes, at the CPU level you would not enable the CLA end of task interrupt.  i.e. comment out this line:

      Interrupt_enable(INT_CLA1_1);

    Q: Are there any more ways to give data to the main CPU. for example, I make an array in CLA and just pass its address to main_CPU?

    A: Any scheme which passes values through the memory can be used.  It is up to you to define.  

    Q: While I am using CLA, I am short of memory. I am using all 8 LS RAMs. Can I increase it further by including other memories?

    A:  Refer to the memory map section in the data manual for the specific device.  Here you will find which memory blocks can be configured for the C28x, the CLA or both.

    Q: I want to store the data using DMA. Is there any DMA example for this platform, using CLA?

    A: Refer to the memory map in the data manual for the specific device.  Here you will find which memory blocks can be accessed by each of the masters: C28x, CLA and DMA.  

    Note: 

    There is an error in the technical reference manual (TRM). It mentions a DMA to CLA message RAM. This feature is not present on the F28004x device. I have filed a ticket to have the document corrected. The data manual memory map is correct.

    Regards

    Lori 

  • Bilal,

    Regarding your last question. There is an error in the technical reference manual (TRM). It mentions a DMA to CLA message RAM. This feature is not present on the F28004x device. I have filed a ticket to have the document corrected. The data manual memory map is correct.

    I wanted to mention that the workshop I linked to earlier is for an older device. It is still a very good introduction to the CLA. A new, very useful, feature on the F28004x is the ability to make task 8 an interruptable background task.

    Regards
    Lori
  • Hi Bilal,

    I haven’t heard from you for a few days, so I’m assuming my response answered your question. If this isn’t the case, please click the "This did NOT resolve my issue" button and reply to this thread with more information. If this thread locks, please click the "Ask a related question" button and in the new thread describe the current status of your issue and any additional details you may have to assist us in helping to solve your questions.

    Regards,
    Lori
  • Thanks Lori!

    Some of the answers were really helpful and resolves my issues. I have been able to to synchronized both and also disabled the CLA post ISR. But I am still facing difficulties with CLA memory. My question/problem is as follow:

    I am using an array that is declared in the CLA memory (RAMLSx). All the RAMLSx's are shared between CPU and CLA.
    MemCfg_setLSRAMMasterSel(MEMCFG_SECT_LS7, MEMCFG_LSRAMMASTER_CPU_CLA1);

    So I assume that the array that I have declared in the CLA is accessible by the CPU as well, if I declare the same array in the cla header file. My entire algorithm is based on this technique. The main CPU collects data from ADC and puts it into an array that is declared in the CLA memory and the cla header file. The CLA then picks sample from that array and process it. In the debug mode, with optimization disabled, I am achieving the right results.

    I also wrote a question regarding CLA in the following thread. You can answer it here as well.

    e2e.ti.com/.../2907892

    Thanks

    Bilal!
  • Thanks Bilal. It looks like Sal is answering your related question on the other thread. I am going to close this thread and let the discussion continue there. If I have misunderstood just post back on this thread and it will reopen.

    Regards
    Lori

  • Hi Lori!

    With full optimization, I was unable to debug the code. So I decided to use the Serial Communication Interface (SCI) and received data on serial monitor (Docklite) in computer. I integrated the SCI code at the bottom of my algorithm to send the final results to serial port on PC. The entire data was accurate.

    So, I conclude that the debug mode does not support optimization (completely) and it was all debugger 's fault.

    Another thing that Sal mentioned i.e. use the volatile keywork. I was using the volatile key word for the respective variables. But I found out that when I declare those variables as volatile, the execution times jumps to 10 - 20 folds (2.5us to 40us). So I eliminated the volatile declaration. Can you further comment on this behaviour? But never the less, without declaring the variables as volatile, I received the exact data at serial port.

    Regards,
    Bilal