TMS320F28377D: DC Event Delaying Using Valley Switching Submodule

Cem Koose

Intellectual 880 points

Part Number: TMS320F28377D

Hi,

I'm trying to add a delay to the DCBEVT2 signal using Valley Switching Submodule to generate a delayed DCEVTFILT.

Capture features of the Valley Switching Submodule is not useful for my application.

In my configuration DCAEVT2 and DCBEVT2 generated by Cmpss comparators. DCAEVT2 signal trips ePWMA immediately.

DCEVTFILT should trip ePWMB's off after some delay. I thought that HWVDELVAL feature of the Valley Switching may be used for this purpose.

DCAEVT2 and DCBEVT2 trips epwmA/B off successfully but I cannot see a delay on the epwmB.

Here is my configuration of valley switching section;

    EPWM_PTR[epwm_num]->DCFCTL.bit.BLANKE = 0; // Blanking window is disabled
    EPWM_PTR[epwm_num]->DCFCTL.bit.SRCSEL = 3; // Source Is DCBEVT2 Signal

    EPWM_PTR[epwm_num]->DCFCTL.bit.EDGEFILTSEL = 1; // Edge Filter Selected
    EPWM_PTR[epwm_num]->DCFCTL.bit.EDGEMODE    = 1; // High to Low Edge, cmpss generates high to low signal
    EPWM_PTR[epwm_num]->DCFCTL.bit.EDGECOUNT   = 0;

    EPWM_PTR[epwm_num]->DCCAPCTL.bit.CAPE      = 0; // TBCTR Counter Capture Disable

    EPWM_PTR[epwm_num]->VCAPCTL.bit.VCAPE      = 0; //0; // Valley capture disable, check!! try 1 didnt worked
    EPWM_PTR[epwm_num]->VCAPCTL.bit.VDELAYDIV = 0; // HWVDELVAL = SWVDELVAL
    EPWM_PTR[epwm_num]->VCAPCTL.bit.EDGEFILTDLYSEL = 1; // HWDELAYVAL delay applied to the edge filter output
    EPWM_PTR[epwm_num]->SWVDELVAL = 1000; // Delay Value

Here is my control path;

Configuration provides HWVDELVAL = SWVDELVAL, so the SWVDELVAL value should adjust the delay.

How can I add delay DCBEVT2 with respect to DCAEVT2?

Regards,

Cem.

over 5 years ago

0 Cem Koose over 5 years ago

Intellectual 880 points

Here is my control path;

0 Nima Eskandari over 5 years ago in reply to Cem Koose

TI__Guru 52010 points

I'll have to get back to you after reviewing some docs.

Nima

0 Cem Koose over 5 years ago in reply to Nima Eskandari

Intellectual 880 points

Thanks,

I want to give some further explanation.
DCBEVT2 and DCAEVT2 are generated by DCAH/DCBH events .
DCBEVT2 and DCAEVT2 sets when DCAH/DCBH low. DCAH/DCBH comes from TRIPIN_X.
Cmpss generates TRIPIN_X at the falling edge. You may check 15.11 Digital Compare (DC) Submodule, Figure 15-49 block diagram to see more clear.

Summary; When cmpss outputs a low signal, DCBEVT2 and DCAEVT2 is triggered.
DCAEVT2 trips epwmA immediately, DCBEVT2 trips epwmB immediately.
I want to add some delay(approximately 3-5usec) epwmB(DCBEVT2 ) tripping with respect to epwmA(DCAEVT2 ).

0 Cem Koose over 5 years ago in reply to Nima Eskandari

Intellectual 880 points

Hi,
Is there any improvement with the issue?

0 Cem Koose over 5 years ago

Intellectual 880 points

I hope someone see this issue and give some support.
I thought that I have provided detailed information on the subject.

0 Nima Eskandari over 5 years ago in reply to Cem Koose

TI__Guru 52010 points

CEM,

I promise you have not been forgotten I have been working my way through the questions this week and I will get back to you very soon.

Nima

0 Nima Eskandari over 5 years ago in reply to Nima Eskandari

TI__Guru 52010 points

Vasudha Bhadoria Cody Watkins have either of you used Valley Switching to catch the error above?

0 Nima Eskandari over 5 years ago in reply to Nima Eskandari

TI__Guru 52010 points

Just a quick question since you have not mentioned it, did you use EVT2SRCSEL to set the source to DCEVTFILT?

0 Cem Koose over 5 years ago in reply to Nima Eskandari

Intellectual 880 points

page:1765, "Figure 15-53. DCBEVT2 Event Triggering" diagram shows the connection to "DCBEVT2.force" signal.
"DCBEVT2.force" is used for shut downs pwms.

DCBCTL[EVT2SRCSEL] = 1; //select DCEVTFILT
DCBCTL[EVT2FRCSYNCSEL] = 1; //Async path

0 Cem Koose over 5 years ago in reply to Nima Eskandari

Intellectual 880 points

I'll give comprehensive epwm configuration;

//------------------------ DCTRIPSEL --------------------------------------//
EPWM_PTR[epwm_num]->DCTRIPSEL.bit.DCAHCOMPSEL = 4; // Cmpss trip signal coming from "TRIPIN4"
EPWM_PTR[epwm_num]->DCTRIPSEL.bit.DCALCOMPSEL = 4;
EPWM_PTR[epwm_num]->DCTRIPSEL.bit.DCBHCOMPSEL = 4;
EPWM_PTR[epwm_num]->DCTRIPSEL.bit.DCBLCOMPSEL = 4;
//-------------------------------------------------------------------------//

//#define TZ_HIZ 0x0
//#define TZ_FORCE_HI 0x1
//#define TZ_FORCE_LO 0x2
//#define TZ_NO_CHANGE 0x3
EPWM_PTR[epwm_num]->TZCTL.bit.TZA = TZ_NO_CHANGE;//TZ1 to TZ6, DCAEVT1/2, DCBEVT1/2Trip Action On EPWMxA
EPWM_PTR[epwm_num]->TZCTL.bit.TZB = TZ_NO_CHANGE;//TZ1 to TZ6, DCAEVT1/2, DCBEVT1/2Trip Action On EPWMxB
EPWM_PTR[epwm_num]->TZCTL.bit.DCAEVT2 = TZ_FORCE_LO; //Digital Compare Output A Event 2 (DCAEVT2) Action On EPWMxA
EPWM_PTR[epwm_num]->TZCTL.bit.DCBEVT2 = TZ_FORCE_LO; //Digital Compare Output B Event 2 (DCBEVT2) Action On EPWMxB

//------------------- EVENT A Qual / EVENT B Qual -------------------------------------//
// Trip Event Polarity Selection
// Active Low Trip Event, cmpss gives low when the overcurrent occurs
EPWM_PTR[epwm_num]->TZDCSEL.bit.DCAEVT2 = 1; // DCAH = low, DCAL = don't care
EPWM_PTR[epwm_num]->TZDCSEL.bit.DCBEVT2 = 1; // DCBH = low, DCBL = don't care
//---------------------------------------------------------------------------------------------------------//

//------------------ Digital Compare Module Event Triggering ---------------------------//
// EVTxSRCSEL => //0: DCxEVT2 / 1: DCEVTFILT
// EVTxFRCSYNCSEL => //0: TBCLK Synch / 1: Async
// DCAEVT2&DCBEVT2 is used for the pwm tripping

EPWM_PTR[epwm_num]->DCACTL.bit.EVT2SRCSEL = 0; // DCAEVT2.force uses DCAEVT2
EPWM_PTR[epwm_num]->DCACTL.bit.EVT2FRCSYNCSEL = 1; // Async

EPWM_PTR[epwm_num]->DCBCTL.bit.EVT2SRCSEL = 1; // DCBEVT2.force uses DCEVTFILT
EPWM_PTR[epwm_num]->DCBCTL.bit.EVT2FRCSYNCSEL = 1; // Async
//--------------------------------------------------------------------------------------//

//----------- Event Filtering & Valley Switching ---------------------------------------//
EPWM_PTR[epwm_num]->DCFCTL.bit.BLANKE = 0; // Blanking window is disabled
EPWM_PTR[epwm_num]->DCFCTL.bit.SRCSEL = 3; // Source Is DCBEVT2 Signal
EPWM_PTR[epwm_num]->DCFCTL.bit.EDGEFILTSEL = 1; // Edge Filter Selected
EPWM_PTR[epwm_num]->DCFCTL.bit.EDGEMODE = 1; // High to Low Edge
EPWM_PTR[epwm_num]->DCFCTL.bit.EDGECOUNT = 0;

EPWM_PTR[epwm_num]->DCCAPCTL.bit.CAPE = 0; // TBCTR Counter Capture Disable

EPWM_PTR[epwm_num]->VCAPCTL.bit.VCAPE = 0; // Valley capture disable
EPWM_PTR[epwm_num]->VCAPCTL.bit.VDELAYDIV = 0; // HWVDELVAL = SWVDELVAL
EPWM_PTR[epwm_num]->VCAPCTL.bit.EDGEFILTDLYSEL = 1; // HWDELAYVAL delay applied to the edge filter output
EPWM_PTR[epwm_num]->SWVDELVAL = 1000; // Delay Value
//--------------------------------------------------------------------------------------//

0 Nima Eskandari over 5 years ago in reply to Cem Koose

TI__Guru 52010 points

I'm going to try this out on my Control Card because I do not see why it wouldnt apply the delay.

0 Nima Eskandari over 5 years ago in reply to Nima Eskandari

TI__Guru 52010 points

I did it. I wrote an example code that does what you originally said.

0 Nima Eskandari over 5 years ago in reply to Nima Eskandari

TI__Guru 52010 points

Okay here is what this code will do. It will set up EPWM1A and 1B and then on the same event, in this case a GPIO routed to TRIPIN1, used by both DCAEVT1 and DCBEVT1. Then DCAEVT1 immdeiate disables EPWM1A. BUT DCBEVT1 is passed through the DCFILT, which uses the Valley Switching Delay, and then that result is used to cause a OSH (one-shot) event at the TZ module. This OST event is used to disable EPWM1B.

Therefore on the same input, both EPWM1A and EPWM1B are disabled but 1B is disabled after a delay.

0 Nima Eskandari over 5 years ago in reply to Nima Eskandari

TI__Guru 52010 points

//! This example configures ePWM1 and ePWM2 as follows
//!  - ePWM1 has TZ1 as one shot trip source
//!
//! Initially tie TZ1 high. During the test, monitor ePWM1 or ePWM2
//! outputs on a scope. Pull TZ1 low to see the effect.
//!
//!  \b External \b Connections \n
//!  - ePWM1A is on GPIO0
//!  - TZ1 is on GPIO25

//
// Included Files
//
#include "driverlib.h"
#include "device.h"

//
// Globals
//
uint32_t  epwm1TZIntCount;

//
// Function Prototypes
//
void initEPWM1(void);
void initTZGPIO(void);
void initEPWMGPIO(void);
__interrupt void epwm1ISR(void);

void main(void)
{
    //
    // Initialize global variables
    //
    epwm1TZIntCount = 0U;

    //
    // Initialize device clock and peripherals
    //
    Device_init();

    //
    // Disable pin locks and enable internal pull-ups.
    //
    Device_initGPIO();

    //
    // Initialize PIE and clear PIE registers. Disables CPU interrupts.
    //
    Interrupt_initModule();

    //
    // Initialize the PIE vector table with pointers to the shell Interrupt
    // Service Routines (ISR).
    //
    Interrupt_initVectorTable();

    //
    // Interrupts that are used in this example are re-mapped to ISR functions
    // found within this file.
    //
    Interrupt_register(INT_EPWM1, &epwm1ISR);

    //
    // Configure ePWM1, and TZ GPIOs
    //
    initEPWMGPIO();
    initTZGPIO();

    //
    // Disable sync(Freeze clock to PWM as well)
    //
    SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_GTBCLKSYNC);
    SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

    //
    // Initialize ePWM1
    //
    initEPWM1();

    //
    // Enable sync and clock to PWM
    //
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

    //
    // Enable interrupts required for this example
    //
    Interrupt_enable(INT_EPWM1_TZ);

    //
    // Enable Global Interrupt (INTM) and real time interrupt (DBGM)
    //
    EINT;
    ERTM;

    //
    // IDLE loop. Just sit and loop forever (optional):
    //
    for(;;)
    {
        NOP;
    }
}
interrupt void epwm1ISR(void){


}

//
// initEPWM1 - Configure ePWM1
//
void initEPWM1()
{
    //
    // Enable DCAEVT1 as one shot trip sources
    //
    //EPWM_enableTripZoneSignals(EPWM1_BASE, EPWM_TZ_SIGNAL_DCAEVT1);
    EPWM_enableTripZoneSignals(EPWM1_BASE, EPWM_TZ_SIGNAL_DCBEVT1);

    EPWM_selectDigitalCompareTripInput(
            EPWM1_BASE, EPWM_DC_TRIP_TRIPIN1, EPWM_DC_TYPE_DCAH);

    EPWM_setTripZoneDigitalCompareEventCondition(
            EPWM1_BASE, EPWM_TZ_DC_OUTPUT_A1, EPWM_TZ_EVENT_DCXH_LOW);

    EPWM_setDigitalCompareEventSource(
            EPWM1_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL);

    EPWM_setDigitalCompareEventSyncMode(
            EPWM1_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_EVENT_INPUT_NOT_SYNCED);


    EPWM_selectDigitalCompareTripInput(
            EPWM1_BASE, EPWM_DC_TRIP_TRIPIN1, EPWM_DC_TYPE_DCBH);

    EPWM_setTripZoneDigitalCompareEventCondition(
            EPWM1_BASE, EPWM_TZ_DC_OUTPUT_B1, EPWM_TZ_EVENT_DCXH_LOW);

    EPWM_setDigitalCompareFilterInput(EPWM1_BASE, EPWM_DC_WINDOW_SOURCE_DCBEVT1);
    EPWM_setDigitalCompareEdgeFilterMode(EPWM1_BASE, EPWM_DC_EDGEFILT_MODE_RISING);
    EPWM_setDigitalCompareEdgeFilterEdgeCount(EPWM1_BASE, EPWM_DC_EDGEFILT_EDGECNT_0);
    EPWM_setValleySWDelayValue(EPWM1_BASE, 6000);
    EPWM_setValleyDelayDivider(EPWM1_BASE, EPWM_VALLEY_DELAY_MODE_SW_DELAY);
    EPWM_setValleyTriggerSource(EPWM1_BASE, EPWM_VALLEY_TRIGGER_EVENT_CNTR_ZERO);
    EPWM_enableValleyCapture(EPWM1_BASE);
    EPWM_enableValleyHWDelay(EPWM1_BASE);
    EPWM_enableDigitalCompareEdgeFilter(EPWM1_BASE);


    EPWM_setDigitalCompareEventSource(
            EPWM1_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);

    EPWM_setDigitalCompareEventSyncMode(
            EPWM1_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_INPUT_NOT_SYNCED);


    //
    // Action on DCAEVT1
    //
    EPWM_setTripZoneAction(EPWM1_BASE,
                           EPWM_TZ_ACTION_EVENT_DCAEVT1,
                           EPWM_TZ_ACTION_LOW);

    EPWM_setTripZoneAction(EPWM1_BASE,
                           EPWM_TZ_ACTION_EVENT_TZA,
                           EPWM_TZ_ACTION_LOW);
    //
    // Action on OSHT TZ B
    //
    EPWM_setTripZoneAction(EPWM1_BASE,
                           EPWM_TZ_ACTION_EVENT_TZB,
                           EPWM_TZ_ACTION_LOW);

    //
    // Enable TZ interrupt
    //
    //EPWM_enableTripZoneInterrupt(EPWM1_BASE, EPWM_TZ_INTERRUPT_OST);

    //
    // Set-up TBCLK
    //
    EPWM_setTimeBasePeriod(EPWM1_BASE, 12000U);
    EPWM_setPhaseShift(EPWM1_BASE, 0U);
    EPWM_setTimeBaseCounter(EPWM1_BASE, 0U);
    EPWM_setTimeBaseCounterMode(EPWM1_BASE, EPWM_COUNTER_MODE_UP_DOWN);
    EPWM_disablePhaseShiftLoad(EPWM1_BASE);

    //
    // Set ePWM clock pre-scaler
    //
    EPWM_setClockPrescaler(EPWM1_BASE,
                           EPWM_CLOCK_DIVIDER_4,
                           EPWM_HSCLOCK_DIVIDER_4);

    //
    // Set up shadowing
    //
    EPWM_setCounterCompareShadowLoadMode(EPWM1_BASE,
                                         EPWM_COUNTER_COMPARE_A,
                                         EPWM_COMP_LOAD_ON_CNTR_ZERO);

    //
    // Set-up compare
    //
    EPWM_setCounterCompareValue(EPWM1_BASE, EPWM_COUNTER_COMPARE_A, 2000U);

    //
    // Set actions
    //
    EPWM_setActionQualifierAction(EPWM1_BASE,
                                  EPWM_AQ_OUTPUT_A,
                                  EPWM_AQ_OUTPUT_HIGH,
                                  EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
    EPWM_setActionQualifierAction(EPWM1_BASE,
                                  EPWM_AQ_OUTPUT_A,
                                  EPWM_AQ_OUTPUT_LOW,
                                  EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);
    EPWM_setActionQualifierAction(EPWM1_BASE,
                                  EPWM_AQ_OUTPUT_B,
                                  EPWM_AQ_OUTPUT_HIGH,
                                  EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
    EPWM_setActionQualifierAction(EPWM1_BASE,
                                  EPWM_AQ_OUTPUT_B,
                                  EPWM_AQ_OUTPUT_LOW,
                                  EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);
}

//
// initTZGPIO - Configure TZ GPIO
//
void initTZGPIO(void)
{
    //
    // Set GPIO 25 as as Asynchronous input with pull up enabled
    //
    GPIO_setPadConfig(25, GPIO_PIN_TYPE_PULLUP);
    GPIO_setPinConfig(GPIO_25_GPIO25);
    GPIO_setDirectionMode(25, GPIO_DIR_MODE_IN);
    GPIO_setQualificationMode(25, GPIO_QUAL_ASYNC);

    //
    // Set GPIO 25 as TZ1 input
    //
    XBAR_setInputPin(XBAR_INPUT1, 25);

    //
    // Configure GPIO 11 as general purpose GPIO for monitoring when the TZ
    // Interrupt has been entered
    //
    GPIO_setPadConfig(11, GPIO_PIN_TYPE_STD);
    GPIO_setPinConfig(GPIO_11_GPIO11);
    GPIO_setDirectionMode(11, GPIO_DIR_MODE_OUT);
}

//
// initEPWMGPIO - Configure ePWM GPIO
//
void initEPWMGPIO(void)
{
    //
    // Disable pull up on GPIO 0 configure them as PWM1A
    //
    GPIO_setPadConfig(0, GPIO_PIN_TYPE_STD);
    GPIO_setPinConfig(GPIO_0_EPWM1A);

    //
    // Disable pull up on GPIO 0 configure them as PWM1A
    //
    GPIO_setPadConfig(1, GPIO_PIN_TYPE_STD);
    GPIO_setPinConfig(GPIO_1_EPWM1B);

}

Use GPIO 25 and connect it to GND after starting the code to cause the TRIPS.

Here is a scope shot of the PWMs and the trigger.

Explanations:

0 Nima Eskandari over 5 years ago in reply to Nima Eskandari

TI__Guru 52010 points

Here is one without the need for you to touch the GPIO. I set it as output and made it go off and trigger at the perfect time to showcase this.

Just set your scope to trigger at the falling edge of GPIO25.

//! This example configures ePWM1 and ePWM2 as follows
//!  - ePWM1 has TZ1 as one shot trip source
//!
//! Initially tie TZ1 high. During the test, monitor ePWM1 or ePWM2
//! outputs on a scope. Pull TZ1 low to see the effect.
//!
//!  \b External \b Connections \n
//!  - ePWM1A is on GPIO0
//!  - TZ1 is on GPIO25

//
// Included Files
//
#include "driverlib.h"
#include "device.h"

//
// Globals
//
uint32_t  epwm1TZIntCount;

//
// Function Prototypes
//
void initEPWM1(void);
void initTZGPIO(void);
void initEPWMGPIO(void);
__interrupt void epwm1ISR(void);

void main(void)
{
    //
    // Initialize global variables
    //
    epwm1TZIntCount = 0U;

    //
    // Initialize device clock and peripherals
    //
    Device_init();

    //
    // Disable pin locks and enable internal pull-ups.
    //
    Device_initGPIO();

    //
    // Initialize PIE and clear PIE registers. Disables CPU interrupts.
    //
    Interrupt_initModule();

    //
    // Initialize the PIE vector table with pointers to the shell Interrupt
    // Service Routines (ISR).
    //
    Interrupt_initVectorTable();

    //
    // Interrupts that are used in this example are re-mapped to ISR functions
    // found within this file.
    //
    Interrupt_register(INT_EPWM1, &epwm1ISR);

    //
    // Configure ePWM1, and TZ GPIOs
    //
    initEPWMGPIO();
    initTZGPIO();

    //
    // Disable sync(Freeze clock to PWM as well)
    //
    SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_GTBCLKSYNC);
    SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

    //
    // Initialize ePWM1
    //
    initEPWM1();

    //
    // Enable sync and clock to PWM
    //
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

    //
    // Enable interrupts required for this example
    //
    Interrupt_enable(INT_EPWM1_TZ);

    //
    // Enable Global Interrupt (INTM) and real time interrupt (DBGM)
    //
    EINT;
    ERTM;

    SysCtl_delay(600000U);
    //
    // IDLE loop. Just sit and loop forever (optional):
    //
    for(;;)
    {
        while(HWREGH(EPWM1_BASE + EPWM_O_TBCTR) < 4000);
        GPIO_writePin(25, 0);
        while(HWREGH(EPWM1_BASE + EPWM_O_TBCTR) > 1000);
        GPIO_writePin(25, 1);
        NOP;
    }
}
interrupt void epwm1ISR(void){


}

//
// initEPWM1 - Configure ePWM1
//
void initEPWM1()
{
    //
    // Enable DCAEVT1 as one shot trip sources
    //
    //EPWM_enableTripZoneSignals(EPWM1_BASE, EPWM_TZ_SIGNAL_DCAEVT1);
    EPWM_enableTripZoneSignals(EPWM1_BASE, EPWM_TZ_SIGNAL_DCBEVT1);

    EPWM_selectDigitalCompareTripInput(
            EPWM1_BASE, EPWM_DC_TRIP_TRIPIN1, EPWM_DC_TYPE_DCAH);

    EPWM_setTripZoneDigitalCompareEventCondition(
            EPWM1_BASE, EPWM_TZ_DC_OUTPUT_A1, EPWM_TZ_EVENT_DCXH_LOW);

    EPWM_setDigitalCompareEventSource(
            EPWM1_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL);

    EPWM_setDigitalCompareEventSyncMode(
            EPWM1_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_EVENT_INPUT_NOT_SYNCED);


    EPWM_selectDigitalCompareTripInput(
            EPWM1_BASE, EPWM_DC_TRIP_TRIPIN1, EPWM_DC_TYPE_DCBH);

    EPWM_setTripZoneDigitalCompareEventCondition(
            EPWM1_BASE, EPWM_TZ_DC_OUTPUT_B1, EPWM_TZ_EVENT_DCXH_LOW);

    EPWM_setDigitalCompareFilterInput(EPWM1_BASE, EPWM_DC_WINDOW_SOURCE_DCBEVT1);
    EPWM_setDigitalCompareEdgeFilterMode(EPWM1_BASE, EPWM_DC_EDGEFILT_MODE_RISING);
    EPWM_setDigitalCompareEdgeFilterEdgeCount(EPWM1_BASE, EPWM_DC_EDGEFILT_EDGECNT_0);
    EPWM_setValleySWDelayValue(EPWM1_BASE, 6000);
    EPWM_setValleyDelayDivider(EPWM1_BASE, EPWM_VALLEY_DELAY_MODE_SW_DELAY);
    EPWM_setValleyTriggerSource(EPWM1_BASE, EPWM_VALLEY_TRIGGER_EVENT_CNTR_ZERO);
    EPWM_enableValleyCapture(EPWM1_BASE);
    EPWM_enableValleyHWDelay(EPWM1_BASE);
    EPWM_enableDigitalCompareEdgeFilter(EPWM1_BASE);


    EPWM_setDigitalCompareEventSource(
            EPWM1_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);

    EPWM_setDigitalCompareEventSyncMode(
            EPWM1_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_INPUT_NOT_SYNCED);


    //
    // Action on DCAEVT1
    //
    EPWM_setTripZoneAction(EPWM1_BASE,
                           EPWM_TZ_ACTION_EVENT_DCAEVT1,
                           EPWM_TZ_ACTION_LOW);

    EPWM_setTripZoneAction(EPWM1_BASE,
                           EPWM_TZ_ACTION_EVENT_TZA,
                           EPWM_TZ_ACTION_LOW);
    //
    // Action on OSHT TZ B
    //
    EPWM_setTripZoneAction(EPWM1_BASE,
                           EPWM_TZ_ACTION_EVENT_TZB,
                           EPWM_TZ_ACTION_LOW);

    //
    // Enable TZ interrupt
    //
    //EPWM_enableTripZoneInterrupt(EPWM1_BASE, EPWM_TZ_INTERRUPT_OST);

    //
    // Set-up TBCLK
    //
    EPWM_setTimeBasePeriod(EPWM1_BASE, 12000U);
    EPWM_setPhaseShift(EPWM1_BASE, 0U);
    EPWM_setTimeBaseCounter(EPWM1_BASE, 0U);
    EPWM_setTimeBaseCounterMode(EPWM1_BASE, EPWM_COUNTER_MODE_UP_DOWN);
    EPWM_disablePhaseShiftLoad(EPWM1_BASE);

    //
    // Set ePWM clock pre-scaler
    //
    EPWM_setClockPrescaler(EPWM1_BASE,
                           EPWM_CLOCK_DIVIDER_4,
                           EPWM_HSCLOCK_DIVIDER_4);

    //
    // Set up shadowing
    //
    EPWM_setCounterCompareShadowLoadMode(EPWM1_BASE,
                                         EPWM_COUNTER_COMPARE_A,
                                         EPWM_COMP_LOAD_ON_CNTR_ZERO);

    //
    // Set-up compare
    //
    EPWM_setCounterCompareValue(EPWM1_BASE, EPWM_COUNTER_COMPARE_A, 2000U);

    //
    // Set actions
    //
    EPWM_setActionQualifierAction(EPWM1_BASE,
                                  EPWM_AQ_OUTPUT_A,
                                  EPWM_AQ_OUTPUT_HIGH,
                                  EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
    EPWM_setActionQualifierAction(EPWM1_BASE,
                                  EPWM_AQ_OUTPUT_A,
                                  EPWM_AQ_OUTPUT_LOW,
                                  EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);
    EPWM_setActionQualifierAction(EPWM1_BASE,
                                  EPWM_AQ_OUTPUT_B,
                                  EPWM_AQ_OUTPUT_HIGH,
                                  EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
    EPWM_setActionQualifierAction(EPWM1_BASE,
                                  EPWM_AQ_OUTPUT_B,
                                  EPWM_AQ_OUTPUT_LOW,
                                  EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);
}

//
// initTZGPIO - Configure TZ GPIO
//
void initTZGPIO(void)
{
    //
    // Set GPIO 25 as as Asynchronous input with pull up enabled
    //
    GPIO_setPadConfig(25, GPIO_PIN_TYPE_STD);
    GPIO_setPinConfig(GPIO_25_GPIO25);
    GPIO_setDirectionMode(25, GPIO_DIR_MODE_OUT);
    GPIO_writePin(25, 1);

    //
    // Set GPIO 25 as TZ1 input
    //
    XBAR_setInputPin(XBAR_INPUT1, 25);

    //
    // Configure GPIO 11 as general purpose GPIO for monitoring when the TZ
    // Interrupt has been entered
    //
    GPIO_setPadConfig(11, GPIO_PIN_TYPE_STD);
    GPIO_setPinConfig(GPIO_11_GPIO11);
    GPIO_setDirectionMode(11, GPIO_DIR_MODE_OUT);
}

//
// initEPWMGPIO - Configure ePWM GPIO
//
void initEPWMGPIO(void)
{
    //
    // Disable pull up on GPIO 0 configure them as PWM1A
    //
    GPIO_setPadConfig(0, GPIO_PIN_TYPE_STD);
    GPIO_setPinConfig(GPIO_0_EPWM1A);

    //
    // Disable pull up on GPIO 0 configure them as PWM1A
    //
    GPIO_setPadConfig(1, GPIO_PIN_TYPE_STD);
    GPIO_setPinConfig(GPIO_1_EPWM1B);

}

0 Cem Koose over 5 years ago in reply to Nima Eskandari

Intellectual 880 points

Thank you very much, Nima. Scope shots shows the results I want.
I will try to reproduce the results, give feedback.

0 Cem Koose over 5 years ago in reply to Nima Eskandari

Intellectual 880 points

Hi Nima,

Thanks again for the detailed work you have done.

I adapted the configuration you made for my project.

Now I have the delayed trip action on epwmB channels.

My application uses three level spwm, so I use epwm1A/1B, epwm2A/B signals for the converter.

In application A channels needs immediate, B delayed tripping action.

Also I use cycle by cyle tripping mode.

Parameters: Switching frequency 10kHz(100usec periode). Delay value 500(500*10nsec=5usec)

Here scope shots;

Trip input not shown above, but its occurring at the point where epwm1A forces low. And then trip signal stays active for a couple of msecs.

As you can see in above pictures, epwmxB channels clears trip after 100usec(10kHz switching frequency) automatically and I see epwmB signals for

5usec wide. This behaviour continues as much as trip signal stays active. Since epwmxA channels shuts immediately, they always stays at low.

Now I'm planning to correct this behaviour, so epwmxB must stay at low during tripping action.

Do you have any suggestion?

Here the code that I use;

    //------------------------ DCTRIPSEL --------------------------------------//
    EPWM_PTR[epwm_num]->DCTRIPSEL.bit.DCAHCOMPSEL = trip_in_select;
    EPWM_PTR[epwm_num]->DCTRIPSEL.bit.DCALCOMPSEL = trip_in_select;
    EPWM_PTR[epwm_num]->DCTRIPSEL.bit.DCBHCOMPSEL = trip_in_select;
    EPWM_PTR[epwm_num]->DCTRIPSEL.bit.DCBLCOMPSEL = trip_in_select;
    //-------------------------------------------------------------------------//

    EPWM_PTR[epwm_num]->TZCTL.bit.TZA     = TZ_FORCE_LO; //TZ1 to TZ6, DCAEVT1/2, DCBEVT1/2Trip Action On EPWMxA
    EPWM_PTR[epwm_num]->TZCTL.bit.TZB     = TZ_FORCE_LO; //TZ1 to TZ6, DCAEVT1/2, DCBEVT1/2Trip Action On EPWMxB

    EPWM_PTR[epwm_num]->TZCTL.bit.DCAEVT2 = TZ_FORCE_LO; //Digital Compare Output A Event 2 (DCAEVT2) Action On EPWMxA
    EPWM_PTR[epwm_num]->TZCTL.bit.DCBEVT2 = TZ_FORCE_LO; //Digital Compare Output B Event 2 (DCBEVT2) Action On EPWMxB

EPWM_PTR[epwm_num]->TZSEL.bit.DCBEVT2 = 1; // Enable DCBEVT2 as a CBC trip source for this ePWM module

EPWM_PTR[epwm_num]->TZDCSEL.bit.DCAEVT2 = 1; // DCAH = low, DCAL = don't care
EPWM_PTR[epwm_num]->TZDCSEL.bit.DCBEVT2 = 1; // DCBH = low, DCBL = don't care

    EPWM_PTR[epwm_num]->DCACTL.bit.EVT2SRCSEL     = 0; // DCAEVT2.force uses DCAEVT2
    EPWM_PTR[epwm_num]->DCACTL.bit.EVT2FRCSYNCSEL = 1; // Async

    EPWM_PTR[epwm_num]->DCBCTL.bit.EVT2SRCSEL     = 1; // DCBEVT2.force uses DCEVTFILT
    EPWM_PTR[epwm_num]->DCBCTL.bit.EVT2FRCSYNCSEL = 1; // Async
    //--------------------------------------------------------------------------------------//

    //----------- Event Filtering & Valley Switching ---------------------------------------//
    EPWM_PTR[epwm_num]->DCFCTL.bit.BLANKE = 0; // Blanking window is disabled, check!!!!, no effect!
    EPWM_PTR[epwm_num]->DCFCTL.bit.SRCSEL = 3; // Source Is DCBEVT2 Signal

    EPWM_PTR[epwm_num]->DCFCTL.bit.EDGEFILTSEL = 1; // Edge Filter Selected
    EPWM_PTR[epwm_num]->DCFCTL.bit.EDGEMODE    = 0; // Low to High Edge
    EPWM_PTR[epwm_num]->DCFCTL.bit.EDGECOUNT   = 0;

    EPWM_PTR[epwm_num]->DCCAPCTL.bit.CAPE      = 1; // TBCTR Counter Capture Enable

    EPWM_PTR[epwm_num]->VCAPCTL.bit.VCAPE      = 1;
    EPWM_PTR[epwm_num]->VCAPCTL.bit.VDELAYDIV = 0; // HWVDELVAL = SWVDELVAL
    EPWM_PTR[epwm_num]->VCAPCTL.bit.EDGEFILTDLYSEL = 1; // HWDELAYVAL delay applied to the edge filter output

    EPWM_PTR[epwm_num]->VCAPCTL.bit.TRIGSEL = 1; // 1: Capture sequence is triggered by CNT_zero event

    EPWM_PTR[epwm_num]->SWVDELVAL = 500; // Delay Value

//--------------------------------------------------------------------------------------//

0 Cem Koose over 5 years ago in reply to Cem Koose

Intellectual 880 points

Hi Nima,
I did it. It works as follows;
Software uses one shot trip to shut down epwmxA/B.
And then inside the epwm ISR, software polls cmpss tripping signal and if there is no tripping coming software clears one shot event using TZCLR[OST] bit.
But I find that TZCLR[DCAEVT1], TZOSTCLR[DCAEVT1], TZCLR[DCBEVT1], TZOSTCLR[DCBEVT1] registers ineffective. Only TZCLR[OST] clears the one shot event and it effects both epwmxA and epwmxB. Can we use the above registers to clear the one shot event for sequentially enabling epwms? For example; first clear epwmxB one shot event and then epwmxA one shot.

0 Nima Eskandari over 5 years ago in reply to Cem Koose

TI__Guru 52010 points

No all oneshots get reenabled when the OST flag is cleared. The other flags are for sw to know what triggered the OST, They are not going to enable the ePWM (thats why you thought they were useless.)

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TMS320F28377D: DC Event Delaying Using Valley Switching Submodule