Hi Expert,
The below is an issue about RAM capacity usage, hope could get your help. Thanks!
1# The "SR171_ACU_DSP_S1.02.map" file is based on the original project. Part of F28335 chips appear abnormally working, with 0x15e unused length in "RAML1_7".
2# The "SR171_ACU_DSP_S1.05_DiaPtr.map" is generated after deleted some large-capacity arrays, with 0x235e unused length in "RAML1_7". And on this condition, all the F28335 systems work normal.
Could you tell me what the reason for this issues, and how to avoid the issue?
Thanks!
MEMORY
{
PAGE 0: /* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */
RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */
RAML0 : origin = 0x008000, length = 0x001000 /* on-chip RAM block L0 */
/* RAML1 : origin = 0x009000, length = 0x001000*/ /* on-chip RAM block L1 */
/* RAML2 : origin = 0x00A000, length = 0x001000*/ /* on-chip RAM block L2 */
/* RAML3 : origin = 0x00B000, length = 0x001000*/ /* on-chip RAM block L3 */
/* ZONE6 : origin = 0x0100000, length = 0x100000*/ /* XINTF zone 6 */
/* ZONE7A : origin = 0x0200000, length = 0x00FC00*/ /* XINTF zone 7 - program space */
// FLASHH : origin = 0x300000, length = 0x008000 /* on-chip FLASH */
// FLASHG : origin = 0x308000, length = 0x008000 /* on-chip FLASH */
// FLASHF : origin = 0x310000, length = 0x008000 /* on-chip FLASH */
// FLASHE : origin = 0x318000, length = 0x008000 /* on-chip FLASH */
// FLASHD : origin = 0x320000, length = 0x008000 /* on-chip FLASH */
// FLASHH_B : origin = 0x300000, length = 0x037F80 /* on-chip FLASH�� ���FLASHB����泤��Ϊ0x80������������CSM_RSVD,BEGIN��CSM_PWL */
// FLASHF_B : origin = 0x310000, length = 0x027F80 /* on-chip FLASH�� ���FLASHB����泤��Ϊ0x80������������CSM_RSVD,BEGIN��CSM_PWL */
FLASHE_B : origin = 0x318000, length = 0x01FF80 /* on-chip FLASH�� ���FLASHB����泤��Ϊ0x80������������CSM_RSVD,BEGIN��CSM_PWL */
// FLASHD_B : origin = 0x320000, length = 0x017F80 /* on-chip FLASH�� ���FLASHB����泤��Ϊ0x80������������CSM_RSVD,BEGIN��CSM_PWL */
// FLASHC_B : origin = 0x328000, length = 0x00FF80 /* on-chip FLASH�� ���FLASHB����泤��Ϊ0x80������������CSM_RSVD,BEGIN��CSM_PWL */
// FLASHC_B : origin = 0x328000, length = 0x010000 /* on-chip FLASH */
// FLASHA : origin = 0x338000, length = 0x007F80 /* on-chip FLASH */
// CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
// BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
// CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
CSM_RSVD : origin = 0x337F80, length = 0x000076 /* Part of FLASHB. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x337FF6, length = 0x000002 /* Part of FLASHB. Used for "boot to Flash" bootloader mode. */
CSM_PWL : origin = 0x337FF8, length = 0x000008 /* Part of FLASHB. CSM password locations in FLASHA */
OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */
ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */
IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */
ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
/* RAMM0 : origin = 0x000050, length = 0x0003B0*/ /* on-chip RAM block M0 */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
/* RAML0_7 : origin = 0x008000, length = 0x008000*/ /* on-chip RAM block L1 */
RAML1_7 : origin = 0x009000, length = 0x007000 /* on-chip RAM block L1 */
/* RAML4 : origin = 0x00C000, length = 0x001000*/ /* on-chip RAM block L1 */
/* RAML5 : origin = 0x00D000, length = 0x001000*/ /* on-chip RAM block L1 */
/* RAML6 : origin = 0x00E000, length = 0x001000*/ /* on-chip RAM block L1 */
/* RAML7 : origin = 0x00F000, length = 0x001000*/ /* on-chip RAM block L1 */
ZONE6 : origin = 0x0100000, length = 0x100000 /* XINTF zone 6 */
/* ZONE7B : origin = 0x20FC00, length = 0x000400*/ /* XINTF zone 7 - data space */
ZONE7 : origin = 0x200000, length = 0x010000 /* XINTF zone 7 - data space */
/* FLASHB : origin = 0x330000, length = 0x008000*/ /* on-chip FLASH */
}
/* Allocate sections to memory blocks.
Note:
codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
execution when booting to flash
ramfuncs user defined section to store functions that will be copied from Flash into RAM
*/
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHE_B PAGE = 0
.pinit : > FLASHE_B, PAGE = 0
.text : > FLASHE_B PAGE = 0
codestart : > BEGIN PAGE = 0
ramdelay : LOAD = FLASHE_B,
RUN = RAML0,
LOAD_START(_RamdelayLoadStart),
LOAD_END(_RamdelayLoadEnd),
RUN_START(_RamdelayRunStart),
PAGE = 0
ramfuncs : LOAD = FLASHE_B,
RUN = RAML0,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
PAGE = 0
csmpasswds : > CSM_PWL PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0
/* Allocate uninitalized data sections: */
.stack : > RAMM1 PAGE = 1
.ebss : > RAML1_7 PAGE = 1
data : > RAML1_7 PAGE = 1
.esysmem : > RAML1_7 PAGE = 1
/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHE_B PAGE = 0
.switch : > FLASHE_B PAGE = 0
.sysmem : > RAML1_7 PAGE = 1
.cio : > RAML1_7 PAGE = 1
/* Allocate IQ math areas: */
IQmath : > FLASHE_B PAGE = 0 /* Math Code */
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
/* Allocate DMA-accessible RAM sections: */
DMARAML4 : > RAML1_7, PAGE = 1
DMARAML5 : > RAML1_7, PAGE = 1
DMARAML6 : > RAML1_7, PAGE = 1
DMARAML7 : > RAML1_7, PAGE = 1
/* Allocate 0x400 of XINTF Zone 7 to storing data */
/* ZONE7DATA : > ZONE7B, PAGE = 1*/
/* .reset is a standard section used by the compiler. It contains the */
/* the address of the start of _c_int00 for C Code. /*
/* When using the boot ROM this section and the CPU vector */
/* table is not needed. Thus the default type is set here to */
/* DSECT */
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS PAGE = 0, TYPE = DSECT
/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
.adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
}
- Rayna
