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CCS/TMS320F280049C: TIDM-1000-Three Phase PFC: Vienna Rectifier - ADC configuration info

Fabrizio Belloni
Prodigy 150 points

Part Number: TMS320F280049C
Other Parts Discussed in Thread: TIDM-1000

Tool/software: Code Composer Studio

Hi,

i need of a clarification regarding the ADC configuration used in the "TIDM-1000-Three Phase PFC: Vienna Rectifier" project provided with "The DigitalPower SDK for C2000™ microcontrollers" software pack.

I'm working with the TIDM-1000 evaluation board using the F280049C-controlCARD.

I studied and tested all the source code provided by TI but i have a lot of doubts regarding the ADC configuration used in the project.

I understood that the "ADC conversion" is triggered by EPWM1A with a frequency of 50KHz but the conversion time required to complete the acquisition from all the ADC channels (ADC-A, ADC-B and ADC-C) is not clear.

I found the following defines but i didn't understand how the ADC_CONV_TIME is calculated. I didn't find any reference document that explain it.

//
// ADC Related
//
#define ADC_TRIG_SOURCE ADC_TRIGGER_EPWM1_SOCA
#define ADC_CONV_TIME ((float)0.000000210)

I'd like to ask you:

- is it possibile to receive an explanation on how the ADCs are configured?

- how is the conversion time calculated? Is it relative to a single SOC of an ADC channel? Or is it the time required to complete the acquisition of all the signals (ADC-A, ADC-B and ADC-C)?

- is the ADC sampling mode simultaneous or sequential?

I red the TMS320x2802x, 2803x Piccolo Analog-to-Digital Converter (ADC) and Comparator Reference Guide (i didn't find the equivalent for the F28004x) 
but I have not been able to clarify my doubts. 

Thank you very much your support.

Fabrizio

 

  • 0
    TI__Genius 16085 points

    Hi Fabrizio,

    According to the 28004x TRM page 1172 clock configuration:
    The core requires approximately 10.5 ADCCLK cycles to process a voltage into a conversion result in 12-
    bit mode.

    So the Conversion time can be calculated based on 10.5*ADCCLK.

    The register ADCCTL2 has a PRESCALE field which determines the
    ADCCLK. The ADCCLK is used to clock the converter.

    In the TIDM-1000, this value is equal to 0.000000210.

    Regards,
    Chen

  • 0 in reply to Chen Jiang ti
    Prodigy 150 points
    Thank you very much for the reply. I undesrtood.
    I found all the info in the TRM page 1309 ADC Timings.

    Thank you for your support.

    Fabrizio