Part Number: TMS320F28069
Tool/software: TI C/C++ Compiler
Hello,
We are using nested interrupt mechanism on different C2000 microcontrollers to implement interrupt prioritization.
Scheme look like this
LowPriority interrupt (every 10 ms based on timer 0)
{
/* Acknowledge interrupt group to receive more interrupts for this group */
s_DrvIT_CorePieCtrlRegs.PIEACK.all = DRV_IT_CORE_PIEACK_GROUP1 ;
/* Enable MedPriority and HighPriority interrupts */
IER = DRV_IT_M_INT3 | DRV_IT_M_INT13
EINT;
/* perform low priority operations */
.
/* and nothing more */
}
MedPriority interrupt (every ms based on timer 1)
{
/* Enable MedPriority and HighPriority interrupts */
IER = DRV_IT_M_INT3
EINT;
/* perform Medium priority operations */
.
/* and nothing more */
}
HighPriority interrupt (XINT based)
{
/* Acknowledge interrupt group to receive more interrupts for this group */
s_DrvIT_CorePieCtrlRegs.PIEACK.all = DRV_IT_CORE_PIEACK_GROUP1 ;
/* high priority operations */
.
.
/* and nothing more */
}
This scheme is used in 2812, 28335 and 28069 without issue, until the errata SPRZ342N (for x28069) mentioning:
"
If the user is enabling interrupts using the EINT instruction inside an interrupt service routine (ISR) in order
to use the nesting feature, then the user must disable the interrupts before exiting the ISR. Failing to do so
may cause undefined behavior of CPU execution.
"
So in our code, it means adding DINT at the end of Medium and low Priority interrupts ? Is it normal in an architectural point of view or rather a workaround ?
What's an "undefined behavior" of CPU execution ? Have you an idea of the occurrence frequency ?
Thanks and regards,
David
