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TMS320F28069: McBSP for SPI - details on frequency limitation

Sebastien Jacquart
Prodigy 50 points
Part Number: TMS320F28069

Hello

I am currently using the Piccolo 28069 McBSP module as SPI to retrieve data from external ADC. 

My DSP is fed with external 20.48MHz clock oscillator, and is working at 56.32MHz with internal PLL.

The operation on McBSP is simple SPI read of single 16bits word, triggered periodically (~400kHz) using PWM + DMA.

DMA capability is the reason why I did not use SPI module but McBSP instead.

I am challenged on the capacity of this system, especially the maximum acquisition speed for which SPI frequency is important contributor (the other being conversion time from ADC)

I found the following information on reference document SPRS698G (page 116):

  • [...] McBSP clock speeds are not greater than the I/O buffer speed limit (20MHz)
  • Maximum McBSP module clock frequency decreases to 10MHz for internal CLKR

 

If I understand correctly, the McBSP in SPI mode (using clock stop mode and CLKR/CLKX generated internally) should thus fall into the 10MHz restriction. 

I performed some tests however up to 18.7MHz (LSPCLK is 56.32MHz and clock divisor for McBSP is 3) and the system seems to work fine. 

I used sinus waveform to feed the ADC, and I am observing the SPI clock at 18.7MHz, with sinus waveform being acquired as expected.

This comes as a bit of a (good) surprise and I would like to better understand the limitation stated in the spreadsheet. In particular I only performed the test in room temperature and did not yet tested the board at max temperature.

Is there something I missed ? What is the nature of this limitation ?

Is the limitation not perceptible due to the short duration of the communication (one single word of 16 bits) ? 

Thank you in advance for your help & best regards

Sebastien

  • 0
    Guru 30330 points
    Hi Sebastian,

    So first, McBSP Timing Requirements table you are referencing is valid in McBSP mode not SPI Mode. I think is has to do with just timings. Not sure much more than that. That requirement is placed on the CLKR when generated from inside the chip (and CLKR is an output I believe). You should be Looking at mcBSP as SPI Master or Slave Timing sections.

    In SPI mode (See McBSP as the SPI Master Section in SPRUH18G) , CLKR is an input from CLKX internally connected and must be LSPCLK/(1+CLKGDV) (SCLKME = 0, CLKSM = 1)


    I think you are operating just out of spec for your configuration. Based on the correct timing table (Table 6-44 of SPRS698G). The Max Speed for SPI master is:
    2*(1/CLKG ) = 2*(1/(LSPCLK/CLKGDV)) = 2/(53.62M/3) = 17.87MHz.

    So 18.7 is just out of past the max speed for SPI master mode. It doesn’t surprise me that it is working in in a restricted lab environment, but you are not guaranteed to have the same behavior outside of the datasheet requirements.

    I hope that is clear. But let me know if it is not.

    Regards,
    Mark
  • 0 in reply to Mark Labbato
    Prodigy 50 points

    Thank you for your answer Mark, it does clarify things.

    It was not clear to me that the limitation on CLKR was for output only. And most of all I had considered the table 6-42 as generic for the McBSP module (including SPI then) and dismissed the 6-44 .

    So this is great news and I am glad to read that the actual constraint is the "2P" condition only when using SPI master mode.

    Side note: my clock is 56.32MHz, not 53.62MHz, so I stand just at the limit from the datasheet. Which is fine for me.

    Best regards,

    Sebastien