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CCS/TMS320F28375D: CPU2 breaking at address "0x3FEC52" with No Debug Information available

Part Number: TMS320F28375D


Tool/software: Code Composer Studio

Hello,

I am using TMS320F28375D SOC, I have programmed it for dual CPU and when I run both the CPU simultaneously, CPU2 crashes with the message "Break at address "0x3FEC52" with no debug information available, or outside the program code." I have experimented and found that both CPU individually works fine when another CPU is on hold i.e CPU2 works fine when CPU1 is on hold and CPU1 works fine when CPU2 is on hold. But both CPU are not working simultaneously.

What could be the probable issue? Could it be (i) IPC (ii) Memory Configuration (iii) Initialization of Clocks or PIE, or it is something other?

Kindly help me with the same to identify and solve the problem. I am also attaching the screenshot of the error.

Thanks in Advance

Shubham