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CCS/TMS320F28379D: HRPWM Clock Frequency Queries

Hasan
Intellectual 405 points
Part Number: TMS320F28379D


Tool/software: Code Composer Studio

Hi,

i had few questions regarding the High Resolution PWM OF f28397D processor. Also i want to confirm few things to avoid confusion regarding clocks for PWM and  HRPWM.

a) What is the default CPU Frequency of F2837D? As per datasheet, it says it is 200Mhz. I haven't written anything on SYSCLKDIVSEL regs and PLL Regs. So assuming it is 200 Mhz, please confirm?

Regarding EPWM:

b) If the default CPU Frequency is 200 Mhz. and if i don't write anything on EPWMCLKDIV which will keep the CPU Frequency (coming from PLLSYSCLK channel) as it is (rather than dividing it by 2) then our EPWMCLK should be 200Mhz as well if i am not wrong, please confirm?

After EPWMCLK, i am using these formulas for TBPRD Reg.

TBCLK Frequency = EPWMCLK/(HSPCLKDIV*CLKDIV)

TBPRD = TBCLK Frequency / 2* PWM Frequency.

Please confirm these formulas because PWM is working fine

Regarding HRPWM:

c) If we see the above clock architecture, it tells that after EPWMCLKDIV, the same clock is feeded to Both HRPWM and EPWM. So if EPWMCLK= 200Mhz, and if we don't use HSPCLKDIV and CLKDIV, then we should be getting TBCLK= 200Mhz for HRPWM but as i tested the HRPWM, even setting HSPCLKDIV and CLKDIV to 1, i am getting TBCLK= 100Mhz, why is it so? am i missing something? do the above formulas for EPWM apply for HRPWM as well? Please point out the conceptual mistakes

Thanks, answers awaited...

  • 0
    TI__Expert 3720 points
    Hi,

    a) Yes CPU Frequency is 200Mhz
    b) EPWMCLK is 100Mhz (and not 200 Mhz). Please refer to device datasheet
    And formula for TBPRD is correct if you are using UP-DOWN counter otherwise '2' in denominator is not required
    c) EPWMCLK is 200Mhz thats why you are getting TBCLK as 100Mhz


    Regards
    Himanshu
  • 0 in reply to Himanshu Chaudhary60
    Intellectual 405 points

    Regarding (b), i understood that it is written in datasheet EPWMCLK= 100 Mhz and HRPWMCLK = 100 Mhz are the maximum values but even though i haven't written anything on SYSCLKDIVSEL regs,PLL Regs, EPWMCLKDIV to divide the CPU Frequency (200 Mhz), where is it getting converted from 200 Mhz to 100 Mhz?

    Regarding (c) you just above said EPWMCLK = 100 Mhz then how has it become 200 Mhz for HRPWM?

  • 0 in reply to Hasan
    TI__Expert 3720 points
    HRPWMCLK is also 100Mhz and not 200Mhz.
  • 0 in reply to Himanshu Chaudhary60
    TI__Guru** 115431 points

    Hi,

    On below point -

     but even though i haven't written anything on SYSCLKDIVSEL regs,PLL Regs, EPWMCLKDIV to divide the CPU Frequency (200 Mhz), where is it getting converted from 200 Mhz to 100 Mhz?

    The default value for EPWMCLKDIV is '1' which means divide by /2 that is why EPWM frq is CPU(SYSCLK)/2 even though you have not configured this register.

    Hope this clarifies it.

    Regards,

    Vivek Singh