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TMS320F28069: how to avoid the unnecessary interruption

Hitoshi Sugawara
Mastermind 19980 points
Part Number: TMS320F28069

Hi Champs,

There seems unnecessary interruption occasionally occurs.
Is there any way to ignore such interruptions?

For example, when the value is changed from 2 to 1 for ETPS[INTPRD] and the counter value is already 1, the interruption occurs just after the ETPS register is written.
I would like to avoid this kind of interruption.

I thought the event for the interruption would be cleared if ETCLR.bit.INT is set to 1.
In this case, it will accept another interruption and the event for the interruption is latched.

Am i making sense?

Best regards,
Hitoshi

  • 0
    TI__Mastermind 27200 points
    Hi Hitoshi,

    The interrupt system is supposed to work that way. To avoid the taking interrupt you would have to disable the interrupt with ETSEL.bit.INTEN, then make the change to ETPS, then re-enable the interrupt.

    ETCLR.bit.INT is 'edge' triggered: writing 1 to it clears existing interrupts but it is not latched, so any later interrupts will occur. The best way to disable interrupts is to do it at the peripheral, as above.

    Regards,

    Richard
  • 0 in reply to Richard Poley
    TI__Mastermind 19980 points
    Hi Richard,
    We have followed the procedure however, the interrupt occurs just after INTEN is enabled.
    It seems that it is not avoidable unless the counter is cleared to 0.

    We will ignore one interruption in the ISR just after the ETPS is changed.
    Thank you for your kind support.
    Best regards,
    Hitoshi