Other Parts Discussed in Thread: C2000WARE
Dear all,
I need to implement 1Msps(at least 500Msps) ADC in my project. The operation allows a break to deal with cached data.
My design is using all 4ch ADC with 1Msps or 500Ksps speed and planning to use DMA to save data to external SDRAM.
I went through the ADC examples in c2000ware. There is an example is using a PWM timer to trigger socs every 50us, using 16 socs to digitize and using DMA to save data.
My thoughts are:
1) I believe I did not catch the essentials of the SOCs yet. why we need so many SOCs? Will socs speed up the converting or the socs are running simultaneously so that we can get multi-converting results at once? In my practice, it seems the SOCs actually cannot be total simultaneous, instead they are in sequence.
2) if SOCs are in sequence say SOC0 -> 1...->SOC15, then what's the advantages here? Why not just run SOC0 15 times?
3) will the timing of every SOC is very accurate? IF the SOCs run time accurate, could I run SOC0 to SOC15 then back to SOC0 .....SOC15 like a circular manner for a continuous acquisition without a timer to trigger.
4) Goes further and back to my application: If the timing of SOCs is accurate, what if I kick off the soc0 then circulate them, make them run and run until there are 500K sampled data is DMAed to external SDRAM.
5) what's your suggestion for my 1Msps (at least 500Ksps) ADC application.
Sorry for many questions, but I believe the key is that I did not understand SOCs very well. Any inputs will be appreciated.
Thanks
