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TMS320F28027: confuse for the execution timing

Part Number: TMS320F28027


Dear

My customer measure the execution timing for below 8 C code about 1.2us.   However from assemble code as below picture, there should be only 3 assemble code for each C code and each assemble code should be 1 cycle timing, and the code is running in RAM base on 60Mhz clock, so we think the total timing for below 8 C code should be 3 x 8 x 16.6ns =  398ns.   We are confuse why measurement is 1.2us?

We use GPIO toggle to measure the execution timing, in order to eliminate the GPIO operation timing, we try to measure the timing with below code at first as A period, then remove the below code to measure again as B period, and finally get the below code execution timing = A - B = 1.2us. 

EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;

EPwm1Regs.AQCTLA.bit.CAD = AQ_SET;
EPwm1Regs.AQCTLB.bit.CAU = AQ_CLEAR;
EPwm1Regs.AQCTLB.bit.CAD = AQ_SET;

EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm2Regs.AQCTLA.bit.CAD = AQ_SET;
EPwm2Regs.AQCTLB.bit.CAU = AQ_CLEAR;
EPwm2Regs.AQCTLB.bit.CAD = AQ_SET;

  • It's not necessarily as simple as the sum of the cycles per instruction--there is the possibility of pipeline conflicts and peripheral frame wait states (see the F28027 datasheet) that can add cycles.

    One thing you can do if this is a big problem is collapse your .bit accesses into .alls. Avoiding the read-modify-writes and back-to-back accesses to the same register may save you some cycles.

        EPwm1Regs.AQCTLA.all = (AQ_CLEAR << 4) | (AQ_SET << 6);
        EPwm1Regs.AQCTLB.all = (AQ_CLEAR << 4) | (AQ_SET << 6);
        EPwm2Regs.AQCTLA.all = (AQ_CLEAR << 4) | (AQ_SET << 6);
        EPwm2Regs.AQCTLB.all = (AQ_CLEAR << 4) | (AQ_SET << 6);

    Whitney