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CCS/TMS320F28379D: Detect XRS reset vs watchdog reset

Part Number: TMS320F28379D


Tool/software: Code Composer Studio

Hello community,

I read "TMS320F28379D: How to identify reset reason from CpuSysRegs.RESC" question/answer and tried to differentiate a XRS reset detection (due to an external signal on XRS pin) vs a watchdog one (auto-generated in software by writing WdRegs.SCSR.all = 0 and WdRegs.WDCR.all = 0) by reading boot status address and RESC register.

Reset with external signal on XRS: after having generated this reset, I read boot status address (0x0000002C) = 0x00004F00 (bit 14 of boot status register = 1, so XRS reset). But if I read WDRSn in RESC register, it is equal to 1. Shouldn't this mean that it is a watchdog reset?

Forced watchdog reset in software: in order to force this type of reset, I wrote WdRegs.SCSR.all = 0 and WdRegs.WDCR.all = 0 instructions in my main and, with the same breakpoint used at the previous point, I read the same exact values of boot status address and RESC register.

At this point my question are:

1) Is there something wrong in what I have done?

2) If not, how can I differentiate a XRS reset (caused by an external signal connected to XRS pin) from a watchdog reset.

 

Thanks a lot!

 

 

  • Hi,

    On the Ist experiment, can you Ist clear the RESC register values and then force the XRSn from external source and check the values. RESC register get reset only by power on reset hence if there was any status flag already set then it'll not be cleared.

    In general if WDRSn bit is set in RESC register then reset was caused by WD only. Please note that WD reset also drives the XRSn so if WD is set, user can ignore the XRSn status.

    Regards,

    Vivek Singh

  • Hi Vivek,

    Many thanks for your prompt answer. Your suggestion works, thanks so much! Now I clear RESC register and, when the next XRS external reset occurs, I can detect it.

    Thanks again for your help