Team,
My customer has the following question:
We’re trying to determine whether the TI Boot ROM will clear all RAM to 0x0000 via RAM INIT after a CPU1.WDRST. Some of the TI documentation states that this will be done, but the Boot ROM flowcharts and source code seem to indicate that this logic includes RESC.XRSn, but not RESC.WDRSn. So we’ve tried tracing Boot execution with emulator to verify, but with the emulator connected, it seems that a CPU Reset (via emulator) leaves RESC=0xC000 (all zeros except 2 pin status monitors). So we are not able to test that WDRST scenario for RAM INIT. And this leaves me wondering if perhaps the CPU1.WDRST event will set both RESC.XRSn and RESC.WDRSn. (We are just now bringing this new board design on-line with first hardware, so we have a ways to go before we can conveniently run tests without emulator.)
Regards,
Aaron
