CCS/TMS320F28379S: How i can config EPWM7​​SYNCOUT signal output by a pin?

Tool/software: Code Composer Studio

I config EPWM7​​SYNCOUT OUTPUT on a GPIO via OUTPUTBAR, but i see a Changeless LOW level on GPIO58. here is my code.

void EPwm7_Init( void ) {
    InitEPwm7Gpio();
        // 比较器输出直接通过XBar连接到EPwm同步信号输入端

        // Interrupts that are used in this example are re-mapped to
        // ISR functions found within this file.
        EALLOW;
        // This is needed to write to EALLOW protected registers
        PieVectTable.EPWM7_INT = &epwm7_isr;
        PieVectTable.EPWM7_TZ_INT = &epwm7_tzint_isr;
        EDIS;

        EALLOW;
        CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
        EPwm7Regs.TBCTL.bit.CLKDIV = 0;
        EPwm7Regs.TBCTL.bit.HSPCLKDIV = 0;

        EPwm7Regs.TBPRD = 50000;            // Set timer period
        EPwm7Regs.TBPHS.all = 0;            // Phase is 0
        EPwm7Regs.TBCTR = 0;

        // Setup TBCLK
        EPwm7Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;    // Count up
        EPwm7Regs.TBCTL.bit.PHSEN = TB_ENABLE;   // when sync comes, TBCTR=TBPHS
        EPwm7Regs.HRPCTL.bit.PWMSYNCSEL = 1;    //  0 PWMSYNC = PRD_eq signal pulse     1 PWMSYNC = CNT_zero signal pulse

        EPwm7Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;  // These bits select the source of the EPWMxSYNCO signal.  0 means EPWMxSYNC TB_SYNC_IN
                                           // TB_SYNC_IN=0 TB_CTR_ZERO
        EPwm7Regs.TBCTL.bit.HSPCLKDIV = 0 ;       // Clock ratio to SYSCLKOUT
        EPwm7Regs.TBCTL.bit.CLKDIV = 0;
        // TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV)
        EPwm7Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
        EPwm7Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;

        // Setup compare
        EPwm7Regs.CMPA.bit.CMPA = 55;  // 40/8*(10^7) = 500ns

        EPwm7Regs.AQCTLA.bit.ZRO = AQ_SET;             // Set PWM1A on CAU    当CTR=0时，强制EPWM1A输出高电平
        EPwm7Regs.AQCTLA.bit.CAU = AQ_CLEAR;           //                     当CTR=CMPA且计数器CTR增计数时，强制EPWM1A输出低电平

        // Active Low PWMs - Setup Deadband
        EPwm7Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
        EPwm7Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
        EPwm7Regs.DBCTL.bit.IN_MODE = DBA_ALL;
        EPwm7Regs.DBRED.bit.DBRED = 5;
        EPwm7Regs.DBFED.bit.DBFED = 5;
        EDIS;

        EALLOW;
        // EPwmXbarRegs
        EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX0 = 0; // CMPSS1.CTRIPH -> MUX0 output -> TRIP4MUXENABLE switch
        EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX0 = 1; // TRIP4MUXENABLE enables MUX0
        EPwmXbarRegs.TRIPOUTINV.bit.TRIP4 = 0; // Active high

                   EPwm7Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_TRIPIN4;        // DCAH = Comparator 1 output DCAH的电平高低由比较器1的输出决定
        //           EPwm7Regs.DCTRIPSEL.bit.DCALCOMPSEL = DC_TZ2;             // DCAL = TZ2                 DCAL的电平高低由TZ2决定
                   EPwm7Regs.TZDCSEL.bit.DCAEVT1 = TZ_DCAH_HI;               // DCAEVT1 =  DCAH High(will become active as Comparator output goes high)
            //                                                                 // DCAH高电平时产生DCAEVT1事件
            //

                   EPwm7Regs.DCACTL.bit.EVT1SRCSEL = DC_EVT_FLT;
                   EPwm7Regs.DCACTL.bit.EVT1FRCSYNCSEL = DC_EVT_ASYNC;  // Take async path
                   EPwm7Regs.DCACTL.bit.EVT1SYNCE = 1;              //  // Sync enabled:

                   // // With DCAEVT1 sync: 166 ns delay. With trip: 31 ns
                   EPwm7Regs.TZCTL.bit.DCAEVT1 = TZ_NO_CHANGE;

                   //===========================================================================
                   // Event Filtering Configuration for DCAEVT1 (disabled for now)
                   EPwm7Regs.DCFCTL.bit.SRCSEL = DC_SRC_DCAEVT1;
                   EPwm7Regs.DCFCTL.bit.BLANKE = DC_BLANK_ENABLE;
                   EPwm7Regs.DCFCTL.bit.PULSESEL = DC_PULSESEL_ZERO;   //Pulse Select For Blanking & Capture Alignment
                   EPwm7Regs.DCFCTL.bit.BLANKINV = 0;

                   EPwm7Regs.DCFOFFSET = 0; // Blanking Window Offset = CMPA(n+1)
                   EPwm7Regs.DCFWINDOW = 70; // Blanking window length - initial value


            EDIS;
            EPwm7Regs.ETSEL.bit.INTSEL = ET_CTRU_CMPA;        // Select INT on Zero event
            EPwm7Regs.ETPS.bit.INTPRD = ET_1ST;             // Generate INT on 1th event
            EPwm7Regs.ETSEL.bit.INTEN = 1;                   // Enable INT

        EALLOW;
            GpioCtrlRegs.GPBGMUX2.bit.GPIO58 = 01;     //
            GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 01;      //   gpio58 -> OUTPUTXBAR1 (O)
            SyncSocRegs.SYNCSELECT.bit.SYNCOUT = 2; // 0：EPWM7​​SYNCOUT
            OutputXbarRegs.OUTPUT1MUX0TO15CFG.bit.MUX14 = 3;
            OutputXbarRegs.OUTPUT1MUXENABLE.bit.MUX14 = 1;

        EDIS;

}