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TMS320F2808: I2C Parameters - Both electrical and Timing

Eric Mac
Intellectual 435 points
Part Number: TMS320F2808

For the I2C I/O (Open-Drain) Electrical specifications I require some insight. The datasheet SPRS230O has three tables  I/O electrical parameters, 1) 5.4, 2) 5.6 and 3) 5.14.4.4. There is some contradictions and clarity is appreciated. Also some I2C timing specifications are required that are not defined in this datasheet.

1) Table 5.4: is Low level sink current specification in this table for "all I/Os except Group2" includes the I2C I/O (SCLA and SDAA)?

2) Table 5.4: is High level sink current specification in this table for "all I/Os except Group2" incorrect since the I2C I/O (SCLA and SDAA) are open-drain and can not source current?

3) Table 5.4: is VIL  specification for "all inputs except X1" includes I2C open drain I/O (0.8V max)? Since this is also specified in table 5.14.4.4?

4) Table 5.4: is VIH specification for "all inputs except X1" includes I2C open drain I/O (2.0V min)? Since this is also specified in table 5.14.4.4?

5) Table 5.6: is VOL voltage max specification includes the I2C open drain I/O (0.4V max) ?

6) Table 5.14.4.4: is VIL  for  I2C open drain I/O (0.3V VDDIO max) the correct value for this parameter? This contradicts item 3?

7) Table 5.14.4.4: is VIH   I2C open drain I/O (0.7V VDDIO min) the correct value for this parameter? This contradicts item 4?

8) Table 5.14.4.4: is VOL  I2C open drain I/O (0.4V) the correct value for this parameter? This agrees with item 4. So, I think this we can assume correct.

9) Where are the Setup and Hold times defined for the SCLA and SDAA signals when data is clocked into the DSP - Please provide?

10) Where are the delay relation ship defined for the SCLA and SDAA signals when data and Clock is output from the DSP - Please provide?

  • 0
    TI__Mastermind 45126 points
    Hi Eric,

    The I2C module in this device meets the Fast Mode spec of the NXP I2C Specification. I suggest you review the spec and its requirements. When GPIOs 32 and 33 are configured for I2C they are open-drain, i.e. bi-directional so neither an input or output.

    To answer your questions:

    1) No. Per the footnote: "Group 2 pins are as follows: GPIO28, GPIO29, GPIO30, GPIO31, TDO, XCLKOUT, EMU0, and EMU1". I2C pins are GPIOs 32 and 33

    2) Correct, they are open-drain signals. I2C lines will only be pulled low.

    3) - 7) Follow the values in 5.14.4.4 per I2C spec.

    8) Yes. This is a requirement in the I2C spec.

    9) You can check the I2C spec for setup and hold times. The I2C module meets the Fast mode spec.

    10) Not sure what you are meaning. Can you explain further?

    Best,
    Kevin
  • 0 in reply to Kevin Allen18
    Intellectual 435 points

    Kevin,

    Thanks for your reply.

    I agree that the I2C signals are NOT in group 2, but entries in table 5.4 states " for all signals NOT in group 2" which would imply the I2C signals pertain for the entry. I believe this is incorrect for Low level sink, high level sink, VIL valves for I2C. Do you Agree?

    For Item 10, when a Master  transmitter, the data should be driven low at some time after the falling edge of clock, what is the max delay? and data shall be held for a time after the rising edge of clock, what is this hold time?

  • 0 in reply to Eric Mac
    TI__Mastermind 45126 points

    Hi Eric,

    These operating conditions are stated for all "I/Os", but the I2C pins are considered open-drain "OD" when configured, not "I/Os". Still, I admit that this could be confusing and additional specification of the I2C OD signals being excluded from these conditions might be necessary.

    I'll create an internal ticket to track and further assess the need for better documentation. Maybe adding a footnote.

    Eric Mac said:
    For Item 10, when a Master  transmitter, the data should be driven low at some time after the falling edge of clock, what is the max delay?

    The 1st timing parameter you're asking about is the "data hold time" (t_HD:DAT). A MAX isn't included in the I2C spec. Only a MIN of 0s is stated.

    Eric Mac said:
    and data shall be held for a time after the rising edge of clock, what is this hold time?

    The 2nd timing parameter you're asking about isn't exactly spec'd either. I suppose it would be the "data set-up time" (t_SU:DAT) plus however long the SCL clock pulse is (which is configured by the user).

    Please look up the I2C NXP spec online for this information.

    Thanks,

    Kevin