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TMS320F280049C: ADC SOC Trigger via Software

Part Number: TMS320F280049C
Other Parts Discussed in Thread: C2000WARE

Hey - I am developing with the F280049C Launchpad.  I have a question on why a delay is required when simultaneously sampling multiple channels.  This appears to be only required when using software to force an SOC.

In my code, I have setup to sample 3 analog inputs on SOC0 (ADCAIN14, ADCBIN7, and ADCCIN7), 3 analog inputs on SOC1 (ADCAIN5, ADCBIN0, and ADCCIN2), and 1 analog input on SOC2 (ADCBIN1).  I setup SOC2 to set ADCINT1 on completion.  I set each Force Start of Conversion Bit and then wait for the ADCINT1 flag.  The problem I ran into is if I don't delay ~2000us between setting the Force bit and reading the ADCINT1 bit I get erratic results.  I noticed in C2000Ware MotorControl SDK the runADCZeroOffsetCalibration() routine  does the same (inserts the 2000us delay).  Why is the delay necessary?  And is this required if the trigger is not from software?

My code for the loop is as follows:

         while (cnt < 512)
         {
             AdcaRegs.ADCSOCFRC1.all = 0x3;                     // Force SOC0 and SOC1 on ADCA
             AdcbRegs.ADCSOCFRC1.all = 0x7;                     // Force SOC0, SOC1, and SOC2 on ADCB
             AdccRegs.ADCSOCFRC1.all = 0x3;                     // Force SOC0 and SOC1 on ADCC
             DELAY_US(2000);                                      
             while (AdcbRegs.ADCINTFLG.bit.ADCINT1 != 1)
             {
             }
             DELAY_US(200);                                      
             IsenA += AdcaResultRegs.ADCRESULT0;
             IsenB += AdccResultRegs.ADCRESULT0;
             IsenC += AdcbResultRegs.ADCRESULT0;
             VsenA += AdcaResultRegs.ADCRESULT1;
             VsenB += AdcbResultRegs.ADCRESULT1;
             VsenC += AdccResultRegs.ADCRESULT1;
             VsenPVDD += AdcbResultRegs.ADCRESULT2;
             cnt += 1;
             AdcbRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;
         }
Thanks!
Brett

  • Hi Brett,

    The recommended method is to poll for the end of conversion for ALL the ADC modules being used in the conversion routine and not rely a fixed delay time before reading the conversion results.

    From your code, only ADCB is polled for the end of conversion (not sure what SOC was configured for ADCB to trigger ADCINT1). Reading the results registers immediately after polling ADCINT1, especially for ADCA and ADCC may or may not give the intended conversion results since you are not sure if ADCA and ADCC conversions have completed.

    Here's a better approach:

    - For ADCA, set ADCINTSEL1N2.INT1SEL to SOC1 (A5), for ADCB set ADCINTSEL1N2.INT1SEL to SOC2 (B1), for ADCC set ADCINTSEL1N2.INT1SEL to SOC1 (C2). I based the SOC to channel mapping from your example above.
    - Modify your polling routine to also add polling for ADCA and ADCC ADCINT1 flag (currently you are only monitoring for ADCB. You can remove the delay statements.
    - Read results associated with all ADC modules and SOCs
    - Clear ALL ADC interrupts ( AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1, AdcbRegs.ADCINTFLGCLR.bit.ADCINT1 = 1 AdccRegs.ADCINTFLGCLR.bit.ADCINT1 = 1)

    Hope this works for you.

    Regards,
    Joseph
  • Hi Brett,

    Have not heard back from you on this topic so I am assuming that you have resolved your issue hence I'm marking this thread as closed.  If you still have questions on this topic, please post it in the forum and someone from our team will get back with you.

    Regards,

    Joseph

  • Hey Joseph - thank you! I was stuck thinking SOC0 and SOC1 would be in lock step across modules so I only needed to poll SOC2. Thank you again,
    Brett