Compiler/TMS320F28335: CpuTimer1 prescale Counter.

Tool/software: TI C/C++ Compiler

Dear TI Hello,

I want to count a period of a signal using CPU timer1,

I want to divide the frequency of the clock counter using the TDDR register,

In the datasheet of the F28335, the description bellow is written:

CPU-Timer Divide-Down. Every (TDDRH:TDDR + 1) timer clock source cycles, the timer counter register

(TIMH:TIM) decrements by one. At reset, the TDDRH:TDDR bits are cleared to 0. To increase the overall timer

count by an integer factor, write this factor minus one to the TDDRH:TDDR bits. When the prescaler counter

(PSCH:PSC) value is 0, one timer clock source cycle later, the contents of the TDDRH:TDDR reload the

PSCH:PSC, and the TIMH:TIM decrements by one. TDDRH:TDDR also reloads the PSCH:PSC whenever the

timer reload bit (TRB) is set by software.

My system freq is 150 MHz, and I want to set the freq of the Timer1 to 50MHz

Does this peace of code is correct?

	CpuTimer1Regs.TPR.all = (3-1);
	CpuTimer1Regs.TPRH.all = 0;

Could you telI me please how I could test the freq division by 3?

Thank you in advance,

S.Tarik,