Hello,
I'm working on the SCI F28069 (RS232) and I'm trying to use a FIFO hardware buffer. I set the RX interrupt to 8 bytes.
The interrupt is successful but only the first 4 bytes are correctly formatted. The next 4 bytes are written with erroneous values that seem random. The frames seem to be received at random very rarely in the right order.
If I configure the interrupt to fire after receiving a byte, it works but I lose all the interest of the FIFO and I multiply the number of interrupts by 8. Maybe I cheat in the settings if you can take a look and explain to me how to handle this FIFO if I do not do it properly.
Thank you very much for your help and support
I am using CCS 6.1.3.00033 with TI compiler V15.12.1.LTS on Ubuntu 16.04 LTS with XDS100V3 JTAG.
The setting code of the SCI is below as well as the code used in the IT.
void scia_fifo_init()
{
EALLOW;
SciaRegs.SCICCR.bit.ADDRIDLE_MODE = 0; // idle-line protocol
SciaRegs.SCICCR.bit.LOOPBKENA = 0; // No loopback
SciaRegs.SCICCR.bit.PARITY = 1; // parity : 0 ODD - 1 : EVEN
SciaRegs.SCICCR.bit.PARITYENA = 1; // parity Enable
SciaRegs.SCICCR.bit.SCICHAR = 7; // 8 char bits
SciaRegs.SCICCR.bit.STOPBITS = 0; // 0: 1 stop bit 1 : Deux bits de stop
SciaRegs.SCICTL1.all = 0x0003;
SciaRegs.SCICTL2.bit.TXINTENA = 0;
SciaRegs.SCICTL2.bit.RXBKINTENA = 1;
SciaRegs.SCICCR.bit.LOOPBKENA = 0; // Enable loop back
SciaRegs.SCIHBAUD = 0x0001;
SciaRegs.SCILBAUD = 0x0024;
//BufferSize
SciaRegs.SCIFFTX.all = 0x0C028;
SciaRegs.SCIFFRX.all = 0x0028;
SciaRegs.SCIFFCT.all = 0x00;
SciaRegs.SCICTL1.all = 0x0023; // Relinquish SCI from Reset
SciaRegs.SCIFFTX.bit.TXFIFOXRESET = 1;
SciaRegs.SCIFFRX.bit.RXFIFORESET = 1;
EDIS;
}
__interrupt void sciaRxFifoIsr(void)
{
Uint16 i=0;
SciLoopCount++;
for(i=0 ;i<8;i++)
{
SCI_rdataA[i] = SciaRegs.SCIRXBUF.bit.RXDT;// .all; // Read data
}
SciaRegs.SCIFFRX.bit.RXFFOVRCLR = 1; // Clear Overflow flag
SciaRegs.SCIFFRX.bit.RXFFINTCLR = 1; // Clear Interrupt flag
PieCtrlRegs.PIEACK.all |= 0x100; // Issue PIE ack
}
