TMS320F28027: What is the ADC sampling rate for the PLL settings that I have, and is it possible to set the PLL to generate ADC clock of 120MHz when not dividing?

Vlad Pavlovic

Part Number: TMS320F28027
Other Parts Discussed in Thread: C2000WARE

Hi, I have two questions regarding the settings of the ADC clock in Piccolo TMS320F28027 device:

1. What is the sampling rate that I am achieving at the TMS320F28027 Piccolo with the following relevant register
settings? Somhow, my calculation does not add up.

I have the external clock at 10MHz.

The PLLSTS PLL status register has the following values:
PLLSTS = 0x0181
PLLSTS.PLLLOCKS = 1
      .PLLLOFF = 0
      .OSCOFF   = 0
      .MCLKOFF = 0
      .DIVSEL   = 3

CLKCTL = 0x0000

XCLK = 0x0000
XCLK.XCLKOUTDIV = 0
XCLK.XCLKINSEL = 0

PCLKCR0 = 0x040D
PCLKCR0.ADCENCLK = 1

PLLCR = 0x000C
PLLCR.DIV = 12

ADCCTL1 = 0x41E4
ADCCTL2 = 0x0002
ADCCTL2.CLKDIN2EN = 0x0
ADCCTL2.ADCNONOVERLAP = 0x1

INTSEL1N2 - 0x2121

ADCSOC0CTL = 0x2908
ADCSOC0CTL.ACQPS = 0x8
ADCSOC0CTL.CHSEL = 0x4
ADCSOC0CTL.TRIGSEL = 0x5

ADCSOC1CTL = 0x2848
ADCSOC1CTL.ACQPS = 0x8
ADCSOC1CTL.CHSEL = 0x1
ADCSOC1CTL.TRIGSEL = 0x5

What I get when calculating is 10MHz x12/1(no division) = 120MHz ADC clock rate, which is 8.36ns periods per cycle.
I am sampling two channels on A, so they are on the same sample/hold circuit. Currently, I am reading only one channel
at the samnpling rate of about 1.44MHz. Since there are two channels, I expect that the actual sampling rate is about 2.88MHz,
which approximately corresponds to ADCCLOCK of 60MHz.

2. Am I making the mistake when assuming that the ADC clock is 120MHz if the PLL based on 10MHz input multiplies by 12, without
clock division? THis higher clock at ADC is never metntioned in TI documents, yet, there is PLL settings without division, that seems to allow it?

What I got is that the internal ADCCLOCK is calculated as 120MHz.
Since it is never mentioned in TI's document, although the PLL could be set in such a way, I wonder if setting the ADCCLOCK to 120MHz is even possible?

over 6 years ago

0 MatthewPate over 6 years ago

TI__Guru* 80180 points

Vlad,

While the PLLCR supports values as you mentioned, the max frequency this device can operate at is 60MHz, as defined in the DS here:

http://www.ti.com/document-viewer/TMS320F28027/datasheet/2802x-clock-table-and-nomenclature-60-mhz-devices-clktab-60mhz#clktab_60mhz

Accordingly, the ADC is capable of running at equal to the system clock at 60MHz as well. I would advise for best performance to also enabled the CLOCKDIV2EN, to clock the ADC at 30MHz. This would reduce the max sampling rate to the mid 1.x MSPS with the use of the NONOVERLAP bit in your code.

No device operation is guaranteed above 60MHz, so when the device is clocked at 120MHz it is in an undefined state and it is not possible to know what logic may have worked correctly or not.

Also, I would suggest looking at the ADC examples in C2000Ware, as proper system initialization examples are shown, such that the order of setting the PLL and enabled peripheral clocks are followed. For example, the PLL has a prescribed lock sequence(checking a bit before enabling the clock to the system), which is not being followed in your code example.

Best,

Matthew

0 Vlad Pavlovic over 6 years ago in reply to MatthewPate

Intellectual 690 points

Thank you Mathew, for all the clarifications.

Sincerely,

Vlad

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TMS320F28027: What is the ADC sampling rate for the PLL settings that I have, and is it possible to set the PLL to generate ADC clock of 120MHz when not dividing?