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Hi
My customer use 28377+ FPGA(spartan6) to extend 2pcs RAM(512K) and Flash(128K), double check with you about the hardware design and software change.
CPU1RAM is enabled by 74LV32
F28377
FPGA
Use CS2 to extend RAM1 RAM2, CS4 is used to extend Flash, read and writing controlled by FPGA
Change example code as below
emif1_16bit_asram.c
Set IO to function 2 as expansion port
GPIO92 used for XA19, No changes in others code.
CCS7.4 MEMOREY observation
1. Write a 32-bit data, only the upper 16 bits have been written in, the address value will be cleared immediately when next statement is executed.
2. When writing to address 0x100002, the address line A0-A4 is 1000; How to configure XA19? is it necessary to set?
3. Emif1ConfigRegs.EMIF1MSEL.all = 0x93A5CE71; After write in, the read out data is 01?
Thanks a lot.
Hi Daniel,
The connection for address lines is not correct. Please see following section ( Figure 25-9. EMIF to 8-bit/16-bit Memory Interface) in device TRM.
For 16bit interface, A0 of external RAM need to be connected to BA1 of EMIF and other address lines need to be adjusted accordingly as shown in figure.
Regards,
Vivek Singh
Hi tlee,
Question 1:
On TI reference, it use EM1OE (GPIO37) as read signal.
Customer use EM1RNW（GPIO33）as read signal for C2000 and FPGA. As below picture.
EM1RNW is high when FPGA is reading, low when not read.
We want to know which GPIO is used to connect with RAM FLASH read signal?
Question 2.
Change HW connection as below.
XA19 is used as the first address line of EM1BA1. GPIO pin is defined as 3. Can we use XA19 as the 20th address or the 21st address line?
Because there are two pieces RAM are used, one is 512K. It need use this address line when FPGA extend, (0x180000-0x1ffffff is used to mapping for the 2nd RAM memory).
0x180000, is the 20th address line is XA19 or XA18? Thanks a lot.
Daniel Fang said:Question 1:On TI reference, it use EM1OE (GPIO37) as read signal.
Customer use EM1RNW（GPIO33）as read signal for C2000 and FPGA.
EM1RNW is high when FPGA is reading, low when not read.
We want to know which GPIO is used to connect with RAM FLASH read signal?
The two signals have different behaviors as defined in the TRM:
OE acts as a STROBE signal, whereas RNW is static for the duration of the memory access. Which signal to use would be determined by the needs of the external component. Standard asynchronous memories typically use OE instead of RNW.
Daniel Fang said:Question 2.XA19 is used as the first address line of EM1BA1. GPIO pin is defined as 3. Can we use XA19 as the 20th address or the 21st address line?
The PINMUX scheme only allows the pin to behave as either EM1A19 or EM1BA1. Manual control of higher address signals (paging) can be achieved through GPIO control.
Hi tlee,
After change hardware according to your advice. As below picture, set all GPIO ports to function 2 for peripheral.
When write address, A19 doesn't work. The address is only increased by +2, the only changed is A0 high/low level.
When write data to RAM, only 0X100000 data has been changed when increase address.
