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CCS/TMS320F28069: In Need of a Clarification for Memory Configuration

İlker
Intellectual 290 points
Part Number: TMS320F28069

Tool/software: Code Composer Studio

Hello Everyone

I am assigned to a project with TMS320F28069 and have been examining documentation for a week now. Yet, I am in need of some clarification about the memory usage.

I am planning to use L3-Ram for CLA Program(since its the only valid memory for CLA Program) and L4-RAM for CLA Data.

Default Project from CCS brings "28069_RAM_lnk.cmd" as default linker cmd file which places .text to L0-L3 and doesn't contain anything about FLASH or CLA. I was thinking even if one wants to run the code from RAM regions, one would need to copy it from FLASH to RAM at start-up before calling any of the functions. Wouldn't RAM loses its content when power is lost ? I don't understand how this can work.

Also,In the linker cmd file "F28069_DCL.cmd" for Digital Control Library,which I'll probably use it later on, there exist memory definitions for CLA's mathTables, Scratch Memory , Program etc. as well as some undefined memory names such as "RAML4L" "CLARAM2" etc.  Is this file usable somehow ?

To Sum it Up, I am looking for a way to configure the linker cmd files  to be used in a Real-Time Control Application.

I would greatly appreciate any help on this topic, Thanks in Advance.

  • 0
    TI__Guru* 92130 points

    İlker said:
    Default Project from CCS brings "28069_RAM_lnk.cmd" as default linker cmd file which places .text to L0-L3 and doesn't contain anything about FLASH or CLA. I was thinking even if one wants to run the code from RAM regions, one would need to copy it from FLASH to RAM at start-up before calling any of the functions. Wouldn't RAM loses its content when power is lost ? I don't understand how this can work.

     Some of TI's linker command files load all of the initialized sections to RAM and then the initialization copies the CLA content to the CLA program RAM.  This is done so you don't have to program the flash.

    • 28069_RAM_CLA_C_lnk

    In a deployed application, the concept is the same except all initialized sections will be programmed into flash instead of RAM - including the CLA program. The CLA program will be copied to the appropriate RAM during the boot-up of the device.  There are example linker command files which include the sections required for CLA.   

    The CLA hands-on-workshop is very good at describing the CLA and how to develop code for it. I think you will find it helpful. Here is the link to the workshop:

    Click here for more CLA FAQs and resources.

    I hope this helps. If this answers your question, please click the green "Verified Answer" button.

  • 0 in reply to Lori Heustess
    Intellectual 290 points
    Hello again Lori, Thanks for your quick response

    Are you saying that the boot-routine automatically copies the content of the Flash, to the RAM locations provided in the linker command file so that the user doesn't need to include anything related to FLASH to the linker cmd ?

    If this is the case, can you point me to a document explaining this process ?
  • 0 in reply to İlker
    TI__Guru* 92130 points

    İlker said:
    Are you saying that the boot-routine automatically copies the content of the Flash, to the RAM locations provided in the linker command file so that the user doesn't need to include anything related to FLASH to the linker cmd ?

    Hello ilker,

    Not exactly.  The application initialization performs the copy from flash into CLA program RAM.  Speed critical C28x code, such as an interrupt service routine, may also be copied from Flash to RAM.   The content in the linker file facilitates this copy by defining symbols corresponding to the start of the code to be copied as well as the length of the copy.  The C28x application code uses this information to perform the copy during application init.

    Resources include:

    I hope this helps. If this answers your question, please click the green "Verified Answer" button.

    Regards

    Lori

  • 0 in reply to Lori Heustess
    TI__Guru* 92130 points

    Hi ilker,

    I haven’t heard from you for about a week, so I’m assuming you were able to resolve your issue. If this isn’t the case, please click the "This did NOT resolve my issue" button and reply to this thread with more information.

    • If this thread locks, please click the "Ask a related question" button and in the new thread describe the current status of your issue and any additional details you may have to assist us in helping to solve your issues.
    • If you have a new question, click the "Ask a new question" button.

    Regards,

    Lori

  • 0 in reply to Lori Heustess
    Intellectual 290 points

    Hello Again Lori

    I have been trying to figure it out by myself for a while, and since the project I am currently working on hasn't come to a point where things related to CLA involves, I did not have the chance to try it, thus I did not post a respond.

    About your previous answer, I understand that the 'CLA Program-StratchPad' and 'PieVectTable' must be copied to the related RAM locations by the user Application, I got that.

    Yet, I am not clear about how .text section is carried to L5-L8 SARAM block. As far as I understand these blocks are only accesible through DMA. So if this is the case

    1.) How and When .text is carried to this RAM Block? Is it performed by the 'cinit()' function or maybe some embdedded Boot-Routine inside Boot ROM? Does this booting mechanism somehow uses DMA to transfer data from FLASH to RAM ? Is Flash DMA Accesible ? .. etc.. ( In my mind Questions keep going like this)
    2.) How C28x fetches program data from a DMA-Access only Memory block ?

    Thanks in advance, İlker.

    Edit: 

    Lori,

    I attached a custom linker cmd file which ı constructed from two different linker.cmd files. I will be glad if you could take a look at it. In addition to this, also the nonbios.cmd is added to the project. I tried to run the project in debug mode, and it is running.What I want is;

    -API Program    --> FLASH Memory.

    -CLA Program   -->L3 SRAM

    -CLA Data         --> L0-L2 SRAM

    -API Data          --> L4 RAM (and if possible also L5-L8)

    Fullscreen my_link.txt Download 
    /*
// TI File $Revision: /main/2 $
// Checkin $Date: January 4, 2011   09:46:02 $
//###########################################################################
//
// FILE:    28069_RAM_CLA_C_lnk.cmd
//
// TITLE:   Linker Command File For F28069 examples that run out of RAM
//
//          This ONLY includes all SARAM blocks on the F28069 device.
//          This does not include flash or OTP.
//
//          Keep in mind that L0,L1,L2,L3 and L4 are protected by the code
//          security module.
//
//          What this means is in most cases you will want to move to
//          another memory map file which has more memory defined.
//
//###########################################################################
// $TI Release: F2806x Support Library v2.04.00.00 $ 
// $Release Date: Thu Oct 18 15:47:20 CDT 2018 $ 
// $Copyright:
// Copyright (C) 2009-2018 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
*/

/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\headers\cmd
//
// For BIOS applications add:      F2806x_Headers_BIOS.cmd
// For nonBIOS applications add:   F2806x_Headers_nonBIOS.cmd
========================================================= */

/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map                                    */

/* Uncomment this line to include file only for non-BIOS applications */
/* -l F2806x_Headers_nonBIOS.cmd */

/* Uncomment this line to include file only for BIOS applications */
/* -l F2806x_Headers_BIOS.cmd */

/* 2) In your project add the path to <base>\headers\cmd to the
   library search path under project->build options, linker tab,
   library search path (-i).
/*========================================================= */

/* Define the memory block start/length for the F2806x
   PAGE 0 will be used to organize program sections
   PAGE 1 will be used to organize data sections

   Notes:
         Memory blocks on F28069 are uniform (ie same
         physical memory) in both PAGE 0 and PAGE 1.
         That is the same memory region should not be
         defined for both PAGE 0 and PAGE 1.
         Doing so will result in corruption of program
         and/or data.

         Contiguous SARAM memory blocks can be combined
         if required to create a larger memory block.
*/

_Cla1Prog_Start = _Cla1funcsRunStart;
-heap 0x400
-stack 0x400

// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are. 

 CLA_SCRATCHPAD_SIZE = 0x200;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start

MEMORY
{
PAGE 0 :

	RAMM0      	: origin = 0x000050, length = 0x0003B0
	BEGIN       : origin = 0x3F7FF6, length = 0x000002     /* Used for "boot to Flash" bootloader mode. */
	OTP         : origin = 0x3D7800, length = 0x000400     /* on-chip OTP */
    FLASH       : origin = 0x3D8000, length = 0x01FF80     /* on-chip FLASH */
    CSM_RSVD    : origin = 0x3F7F80, length = 0x000076     /* Program with all 0x0000 when CSM is in use. */    
    CSM_PWL     : origin = 0x3F7FF8, length = 0x000008     /* CSM password locations in FLASH */
	
	FPUTABLES   : origin = 0x3FD860, length = 0x0006A0     /* FPU Tables in Boot ROM */
    IQTABLES    : origin = 0x3FDF00, length = 0x000B50     /* IQ Math Tables in Boot ROM */
    IQTABLES2   : origin = 0x3FEA50, length = 0x00008C     /* IQ Math Tables in Boot ROM */
    IQTABLES3   : origin = 0x3FEADC, length = 0x0000AA	   /* IQ Math Tables in Boot ROM */

    ROM         : origin = 0x3FF3B0, length = 0x000C10     /* Boot ROM */
    RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
	
	RAML3		: origin = 0x009000, length = 0x001000  	//	CLA Program

	RAML8       : origin = 0x012000, length = 0x002000	   	//	Ram Functions


PAGE 1 :

   /* Part of M0, BOOT rom will use this for stack */
   BOOT_RSVD   	        : origin = 0x000002, length = 0x00004E
   /* on-chip RAM block M1 */
   RAMM1       	        : origin = 0x000480, length = 0x000380     
   CLARAM0              : origin = 0x008800, length = 0x000400	// CLA RAM
   CLARAM1              : origin = 0x008C00, length = 0x000400
   CLARAM2				: origin = 0x008000, length = 0x000800
   /* on-chip RAM block L4-L7 */
   RAML4            	: origin = 0x00A000, length = 0x002000 	// C28 RAM
   RAML5              	: origin = 0x00C000, length = 0x002000	// DMA RAM
   RAML6       	    	: origin = 0x00E000, length = 0x002000
   RAML7       			: origin = 0x010000, length = 0x002000


   CLA1_MSGRAMLOW       : origin = 0x001480, length = 0x000080
   CLA1_MSGRAMHIGH      : origin = 0x001500, length = 0x000080


}


SECTIONS
{
	/* Allocate program areas: */
    .cinit              : > FLASH       PAGE = 0
    .pinit              : > FLASH       PAGE = 0
    .text               : > FLASH       PAGE = 0
    codestart           : > BEGIN       PAGE = 0
    ramfuncs            : LOAD = FLASH      PAGE = 0,
                          RUN  = RAML8   PAGE = 0,
                          LOAD_START(_RamfuncsLoadStart),
                          LOAD_SIZE(_RamfuncsLoadSize),
                          LOAD_END(_RamfuncsLoadEnd),
                          RUN_START(_RamfuncsRunStart)

    csmpasswds          : > CSM_PWL     PAGE = 0
    csm_rsvd            : > CSM_RSVD    PAGE = 0

   Cla1Prog        : > RAML3,
                     LOAD_START(_Cla1funcsLoadStart),
                     LOAD_END(_Cla1funcsLoadEnd),
                     LOAD_SIZE(_Cla1funcsLoadSize),
                     RUN_START(_Cla1funcsRunStart),
                     PAGE = 0
   
   Cla1ToCpuMsgRAM  : > CLA1_MSGRAMLOW,   PAGE = 1
   CpuToCla1MsgRAM  : > CLA1_MSGRAMHIGH,  PAGE = 1
   Cla1DataRam0		: > CLARAM0,		  PAGE = 1
   Cla1DataRam1		: > CLARAM1,		  PAGE = 1
   Cla1DataRam2		: > CLARAM2,		  PAGE = 1

   CLA1mathTables	: > CLARAM1,
                      LOAD_START(_Cla1mathTablesLoadStart),
                      LOAD_END(_Cla1mathTablesLoadEnd), 
                      LOAD_SIZE(_Cla1mathTablesLoadSize),
                      RUN_START(_Cla1mathTablesRunStart),
                      PAGE = 1

   CLAscratch       : 
                     { *.obj(CLAscratch)
                     . += CLA_SCRATCHPAD_SIZE;
                     *.obj(CLAscratch_end) } > CLARAM0,
					 PAGE = 1


   .stack           : > RAML4,     PAGE = 1
   .ebss            : > RAML4,     PAGE = 1
   .esysmem         : > RAML4,     PAGE = 1
   .sysmem          : > RAML4,     PAGE = 1
   .cio             : > RAML4,     PAGE = 1
   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
    /* Initalized sections go in Flash */
    /* For SDFlash to program these, they must be allocated to page 0 */
    .econst             : > FLASH       PAGE = 0
    .switch             : > FLASH       PAGE = 0
    .args               : > FLASH       PAGE = 0

#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
    .TI.ramfunc         : {} LOAD = FLASH    PAGE = 0,
                             RUN  = RAML8    PAGE = 0,
                             table(BINIT)
#endif
#endif

    /* Allocate IQ math areas: */
    IQmath              : > FLASH       PAGE = 0            /* Math Code */
    IQmathTables        : > IQTABLES    PAGE = 0, TYPE = NOLOAD

    /* Allocate FPU math areas: */
    FPUmathTables       : > FPUTABLES   PAGE = 0, TYPE = NOLOAD

    /*
     *  Uncomment the section below if calling the IQNexp() or IQexp()
     *  functions from the IQMath.lib library in order to utilize the
     *  relevant IQ Math table in Boot ROM (This saves space and Boot ROM
     *  is 1 wait-state). If this section is not uncommented, IQmathTables2
     *  will be loaded into other memory (SARAM, Flash, etc.) and will take
     *  up space, but 0 wait-state is possible.
     */
    /*
    IQmathTables2       : > IQTABLES2   PAGE = 0, TYPE = NOLOAD
    {
        IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
    }
    */

    /*
     *  Uncomment the section below if calling the IQNasin() or IQasin()
     *  functions from the IQMath.lib library in order to utilize the
     *  relevant IQ Math table in Boot ROM (This saves space and Boot ROM
     *  is 1 wait-state). If this section is not uncommented, IQmathTables2
     *  will be loaded into other memory (SARAM, Flash, etc.) and will take
     *  up space, but 0 wait-state is possible.
     */
    /*
    IQmathTables3       : > IQTABLES3   PAGE = 0, TYPE = NOLOAD
    {
        IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)
    }
    */
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

  • 0 in reply to İlker
    TI__Guru* 92130 points

    İlker said:
    Yet, I am not clear about how .text section is carried to L5-L8 SARAM block. As far as I understand these blocks are only accesible through DMA. So if this is the case

    The memory map in the Data Manual shows the memory blocks and access.    I can see why this may be confusing - at the top of the memory map there is a column that says "data space" and one that says "program space".  These correspond to the C28x CPU access capabilities.  For L5-L8, the C28x has access in both data space and program space.  In addition the DMA has access as indicated as a note in the memory block itself (i.e. DMA RAM 0). 

    İlker said:
    1.) How and When .text is carried to this RAM Block? Is it performed by the 'cinit()' function or maybe some embdedded Boot-Routine inside Boot ROM? Does this booting mechanism somehow uses DMA to transfer data from FLASH to RAM ? Is Flash DMA Accesible ? .. etc.. ( In my mind Questions keep going like this)

    The CLA program (i.e. CLA text) is placed into its own section Cla1Prog.  The C28x then performs the copy from flash to the CLA program RAM.  CLA program RAM is the L3 block.  Please refer to the resources I mentioned previously.  These describe the CLA initialization sequence as well as the compiler symbols.

    İlker said:
    2.) How C28x fetches program data from a DMA-Access only Memory block ?

    Please see response above.  The memory access is not restricted to only the DMA. 

    Regards

    Lori

  • 0 in reply to İlker
    TI__Guru* 92130 points

    İlker said:
    I attached a custom linker cmd file which ı constructed from two different linker.cmd files. I will be glad if you could take a look at it. In addition to this, also the nonbios.cmd is added to the project. I tried to run the project in debug mode, and it is running.What I want is;

    For the CLA this is fine with the emulator connected.  When y ou want to run standalone the CLA program (Cla1Prog) will need to be loaded to Flash and then copied to RAM using the symbols defined in the linker command file (Cla1functsLoadStart etc..).

    Regards

    Lori

  • 0 in reply to Lori Heustess
    Intellectual 290 points
    Thank you for you attention Lori, Have a nice weekend , İlker.