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TMS320F280049: ADCCLK PRESCALE

CK Ting
Prodigy 70 points

Part Number: TMS320F280049

Hi,

based on the F28004x technical manual, page 1310, table 13-8 ADC Timings in 12-bit mode.

understand that ADCCLK can vary by using different ADCCTL2 prescale value, the AD conversion time will increase.

can help to explain how to chose an appropriate ADCCLK  ?

for example, SYSCLK = 10nsec, set ACQPS=14, then the ADC S+H time is 150nsec.

can explain what is the advantage/disadvantage when I set ADCCTL2 = 0 (conversion time is 110nsec)  compare to when I set ADCCTL2 = 6 (conversion time is 410nsec)

will that affect the stability of the AD count ?

Thanks

CK Ting

  • 0
    TI__Guru 60865 points

    Hi CK,

    There is a maximum ADC clock rate (50MHz) specified in the datasheet:

    You want to use the clock divider to get as close to the max clock rate as possible without going over.  Assuming you are operating the device at 100MHz, you'd always want to pick /2 (the ADC clock isn't free-running, so there are no expected power savings for running it slower). 

    Running the ADC clock faster than the maximum rated frequency will result in erroneous and unpredictable results. 

  • 0 in reply to Devin Cottier
    Prodigy 70 points

    Hi Devin,

    Thanks for the reply, so the recommendation is to pick the ADCLK to run at 50MHz.

    and there is no advantage to pick ADCLK to run at 25MHz if I can chose, no better accurate AD count, right?

    Thanks.

    Regards,

    CK

  • 0 in reply to CK Ting
    TI__Guru 60865 points

    Hi CK,

    Yes, that is correct; there is no advantage to running the ADC slower than 50MHz.