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TMS320F280049: Peripheral frames wait states

Francois Charlot
Mastermind 29547 points

Part Number: TMS320F280049

Hi Champs,

Feels silly, but I could not find a table anywhere that lists the read and write wait states when accessing the various peripheral frames. I could find such a table for older products (e.g., the F2833x, table 6-26), but not for F28004x.

Thanks,
François.

  • 0
    TI__Guru** 116421 points

    Hi Francois,

    I'll check why this table was removed from device document but the access time for different peripheral frame on F280049 should be same on F280049 device as given in F2833x documents because CPU architecture has not changed. I'll confirm this again with our design team and get back to you.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    TI__Mastermind 28275 points
    Hi Francois,

    Vivek is on vacation at the moment and he will reply to you when he gets back. Thanks.
  • 0 in reply to Frank Ankapong
    TI__Guru** 116421 points

    Hi,

    I am back but still waiting for the response from design team. Should have update before end of this week.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    TI__Guru** 116421 points

    Hi François,

    I have confirmed with design team that access time is same on F28004x as F28335 device for peripheral frames. Please note that on F28004x device we have arbitration scheme between CPU/CLA and DMA hence if access are made from different masters at same time then accesses will be stalled for more than one cycle based on the arbitration. Also note that WRITE access are posted write (buffered) hence if there are back-2-back write then 2nd write will have 1 wait-state while buffered write is in progress.

    Regards,

    Vivek Singh