CCS/LAUNCHXL-F28379D: ADC values reading incorrect

Hi Sangamesh,

You can find the formula for converting ADC readings to voltages in the device TRM in the section "Expected Conversion Results":

http://www.ti.com/lit/ug/spruhm8h/spruhm8h.pdf

This will boil down to (RESULT/4096)*VREFHI in 12-bit mode.   I think the formula you have is equivalent if VREFHI = 3.0V, which should be the case for your EVM.  

Note that ADC channels A0, A1, and B1 have a parasitic pull-down of about 50k as specified in the device datasheet "Signal Descriptions" table.

In general, ADC inputs are not high impedance, but instead should be modeled as a switched-capacitor network (see DS section "ADC Input Models"); you should be very careful when driving them with anything other than a low impedance and high bandwidth buffer (usually an op-amp).  Typical driving setup for this ADC in 12-bit mode might be an op-amp with >1MHz BW, series R < 50ohms, and input capacitor on the ADC pin of around 220pF.  You can get away with no op-amp and a higher resistive impedance (say maybe a couple kohm or so) if you use a very large capacitor on the ADC input pin (roughly > 100nF).  This will come at the expense of achievable sample rate on that particular channel.  

When your input driver is not ideal, another way you can compensate is by increasing the S+H window duration (at the expense of sample rate / latency). This is controlled by the ACQPS setting of the SOC configuration in the SW.  You might take a look at the "Choosing an Acquisition Window Duration" section of the TRM, while noting that the equivalent impedance of your voltage divider is R1 || R2.  

Thank you for your answer

As per your answer , I have worked on ADC  

          Test No 1. by using Op-amp buffer amplifier (with capacitor and without capacitor at ADC input)

          Test No 2. by changing ACQPS value

Test No 1. 

 

Results: 

So As we can see in those results, Readings are good if I use capacitor across ADC and also we can notice one more thing that If I don't use capacitor ADC values are more than what is expected

1. Why ADC values are reading more if I don't use capacitor? 

2. What is the use of capacitor at ADC input and how it helps in ADC?

3. If sample window (ACQPS)  value is 15 for my application, What happens to ADC values if I keep ACQPS value more than 15 (say 20 or 50)?

I have these questions in my mind?

Hi Sangamesh,

Great job on the thorough investigation!

One thing to note is that in the case of the op-amp circuit, you might need to be careful driving the large capacitor (100nF) directly; it is quite possible that the op-amp is not stable driving that large of a load. The result of this might be oscillations on top of your DC value. For the op-amp circuit, I'd suggest your start your evaluation with Rs = 30 ohms and Cs = 220pF.

In the case of the op-amp circuit with no capacitor, the issue is that you switch-in a capacitive load (the internal ADC S+H capacitor) and cause a step-function for the voltage on the op-amp output. It takes quite some time for the op-amp to recover from this. The recommended capacitor when using an op-amp is about 20*Csh; this keeps the step-function voltage on the ADC input pin to less than 1/20 Vin (5%) which prevents the op-amp from having to slew and settle wildly across the full voltage range.

In the op-amp case you may want to adjust up the S+H time, but sampling rate can be very high.

As for the charge-sharing case (where you have 100nF on the pin with no op-amp), what is your sampling rate on the pin? If the sampling rate is too fast, the external capacitor will not be sufficiently recharged between samples.

Overall in the charge-sharing case (large cap, no op-amp) you can use the minimum S+H time, but sampling rate may need to be limited.

Have a read through these app notes to get more of the 'why' and 'how' of designing the ADC input network.

www.ti.com/.../slyp166.pdf
www.ti.com/.../spna088.pdf
e2e.ti.com/.../4478.PA_2D00_001--Optimize_5F00_SAR_5F00_converter_5F00_design-REV-b.pdf