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Original question:

CCS/TMS320F280049C: no 280049C but only 280049M in CCS7.2

CCS/TMS320F280049C: TMS320F280049C PWM problem

Jeremy CHU
Prodigy 190 points

Part Number: TMS320F280049C

Tool/software: Code Composer Studio

Hi,

I want to do variable frequency control,but I concern about the TBPRD&CMPA load time.

If load in time base count to zero,and the programmed just write the TBPRD to the shadow register at time base count to one (CMPA not write yet),and time base count to zero,

the TBPRD&CMPA load from shadow register to active register,but CMPA not the new value, so PWM could be all high, like the figure.

Does TI release some function can write CMPA&TBPRD to shadow register at the same ime or something like that to solve this problem?

  • 0
    TI__Genius 10845 points

    Hi,

    I don't think it should create a problem if the load event for both CMPA & TBPRD is same and CMPA & TBPRD are updated one after the other as the CPU would be working at much faster rate than the PWM counter. You can configure the same load event for shadow to active register copy for CMPA & TBPRD. Refer to TBCTL & CMPCTL register description in device TRM for more details.

    Thanks
    Vasudha

  • 0 in reply to Vasudha Bhadoria
    Prodigy 190 points

    Time base counter = 1 => TBPRD = 50

    Time base counter = 0 => CMPA = 25, load event occur

    After TBPRD&CMPA load event, the TBPRD is the new value, but the CMPA is the old value, so TBPRD is equal to CMPA, PWM should be all high, is

    there any way to comfirm the TBPRD&CMPA can write into shadow register in the same time?

    Or can you explaon why this problem will not happen. Thanks

  • 0 in reply to Jeremy CHU
    Prodigy 190 points
    I want update CCS in
    processors.wiki.ti.com/.../Download_CCS
    but the web seems broken.
    www.ti.com/.../CCSTUDIO
    this web also.
  • 0 in reply to Jeremy CHU
    Prodigy 190 points
    I have not heard back from you, please let us know if you still helping us to solve this issue?
  • 0 in reply to Jeremy CHU
    TI__Genius 10845 points

    Hi,

    What do you mean by the below statement?

    Time base counter = 1 => TBPRD = 50

    Time base counter = 0 => CMPA = 25, load event occur

    Shadow mode can be enabled for both TBPRD and CMPx registers. If the load even is same for both, once the CPU has written the new values, these will be loaded at the same time in both TBPRD & CMPA.

    Check the description for TBCTL[PRDLD] & CMPCTL[LOADAMODE] bits in device TRM.

    Thanks

    Vasudha

  • 0 in reply to Vasudha Bhadoria
    Prodigy 190 points
    Time base counter = 1 => TBPRD = 50

    Time base counter = 0 => CMPA = 25, load event occur

    Means time base counter equal 1, TBPRD write in shadow register. Time base counter equal 0, CMPA write in shadow register.

    I don't know when time base counter equal 0, it will write CMPA in shadow register first, and load it to active.

    Or it will load shadow register to active immediately.

    I know it will load TBPRD&CMPA from shadow register into active register.

    But I want to confirm the TBPRD&CMPA can write into shadow register in the same time?
  • 0 in reply to Jeremy CHU
    TI__Genius 10845 points
    Hi,

    If the load event is configured same for both TBPRD & CMPA, shadow to active register load will happen at the same time only.
    You can also use global load feature to make sure that these active registers are loaded at the same time.

    I don't think it is possible to write both TBPRD & CMPA shadow registers at the same time.

    Thanks
    Vasudha