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TMS320F28069: Fast Data Transfer.. C28x or DMA ?

İlker
Intellectual 290 points
Part Number: TMS320F28069
Other Parts Discussed in Thread: C2000WARE

Hello Everyone,

I am currently working on a Project involving 3-Phase Power Control and my peripheral setup is as explained below;

- 90 MHz SYS Clock.

- 45MHz ADC Clock, 25 ADC Cycles for S/H circuitry.(Ref. Manual says it takes approximately 866nS  for one Conversion to Complete with this settings.)(Though I might lower S/H Window in future)

- ePWM with frequency of 10Khz,Triggering total of 6 Measurements, 3 for Currents and 3 for Voltages.

- Sampled Signal is 50Hz Power Grid. Meaning for each measurement I will have 200 samples for each periode.

- I Configured the ADC SOC Channels so that the measurement data  lies on adjacent memory blocks  [ADCRESULTREG2 to ADCRESULTREG7] 

Now, What I have been planning is to configure the ADCs to trigger spesific CLA Tasks that performs Control Logic, and at the same time  move the Measurement Data(6*200 Samples) elsewhere in the RAM in an organized fashion so that the C28x can Analyze the drawn current/voltage. I was planning to configure the DMA to burst 6 WORDs of conversion data whenever 6 Measurements are taken(10KHz) and when all 200 Samples is done,Inside  DMA Transfer Completed interrupt  a SW Flag would be raised so that the C28x can analyze the input data. Yet I have never used the DMA before, and In some threads I have seen claims of C28x is actually being faster than the DMA in terms of data transfer speed and it got me confused.

Would using the DMA be necessary / efficient in this scenerio? And if that is not the case  Should I simply stick with ADC-EOC Interrupts to perform data movement ? 

I would greatly appreciate any other suggestions too, Thanks in Advance, İlker.

  • 0
    TI__Genius 17315 points
    İlker,

    As you may already know, the DMA has a maximum of 32 words/burst (i.e. burst size is a 5-bit ‘N-1’ value) and the transfer size maximum is a 16-bit ‘N-1’ value (which exceeds any practical requirements). The throughput is 4 cycles/word plus 1 cycle delay to start each burst. Note that 32-bit transfer doubles throughput. Please see the TRM section 11.4 for additional pipeline timing and throughput details, and section 11.5 for CPU arbitration. Typically, DMA activity is independent of the CPU activity, and the DMA has priority over CPU.

    Please see the F28069 workshop at:

    processors.wiki.ti.com/.../C2000_Archived_Workshops

    Module 9 covers the DMA and the lab exercise uses the DMA to service the ADC. Also, you might be interested in Module 10 which covers the CLA.

    Additional example code for the DMA and CLA can be found in C2000Ware:

    C:\ti\c2000\C2000Ware_<version>\device_support\f2806x\examples\c28\dma_gsram_transfer\cpu1\dma_ex1_gsram_transfer.c

    I hope this helps. If this answers your question, please click the green "Verified Answer" button. Thanks.

    - Ken
  • 0 in reply to Ken Schachter
    Intellectual 290 points
    Hello Ken,

    More than DMA Specs, I wondered whether it makes sense to use DMA for such- not too big- amount of transfer or not. Would the effort required to work it properly worth the benefits..

    Anyways,I decided to give it a shot since approximately 130kW/seconds transfer-rate is needed in the project. I thought even if the DMA could be little slower than the CPU(which I do not know if this is the case), not using any interrupt /C28x would be much better. I am quite satisfied with the outcome for now. Thank you for your attention.

    İlker.
  • 0 in reply to İlker
    TI__Genius 17315 points
    İlker,

    This is a system design specific question. You would need to determine if the extra overhead is worth using the DMA. As you know, a benefit in favor of using the DMA is it will perform the transfer without intervention from the CPU.

    - Ken