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TMS320F28377S: ADCs are triggered by Timer0

Part Number: TMS320F28377S

Hi,

i try to read ADC0 to ADC3 channes which are triggered by Timer0.

When i trig just ADC0 by Timer0 i can read true value BUT when i trig ADC0 and ADC1 , i measure wrong value on ADCRESULT0 and additionaly although there is not any analog value on ADC1, iread some values on ADCRESULT1.

void SetupADCSoftware()
{
    Uint16 acqps;
    acqps = 14;
    EALLOW;
    AdcaRegs.ADCSOC0CTL.bit.CHSEL = 0;  //SOC0 will convert pin A0
    AdcaRegs.ADCSOC0CTL.bit.ACQPS = acqps; //sample window is acqps +
    AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 1;

    AdcaRegs.ADCSOC1CTL.bit.CHSEL = 1;  //SOC1 will convert pin A1
    AdcaRegs.ADCSOC1CTL.bit.ACQPS = acqps; //sample window is acqps +    //1 SYSCLK cycles
    AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = 1;

    AdcaRegs.ADCSOC2CTL.bit.CHSEL = 2;  //SOC2 will convert pin A2
    AdcaRegs.ADCSOC2CTL.bit.ACQPS = acqps; //sample window is acqps +
    AdcaRegs.ADCSOC2CTL.bit.TRIGSEL = 1;

    AdcaRegs.ADCSOC3CTL.bit.CHSEL = 3;  //SOC3 will convert pin A3
    AdcaRegs.ADCSOC3CTL.bit.ACQPS = acqps; //sample window is acqps +
    AdcaRegs.ADCSOC3CTL.bit.TRIGSEL = 1;

    AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 0x3; //end of SOC3 will set INT1 flag
    AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1;   //enable INT1 flag
    AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //make sure INT1 flag is cleared
    EDIS;
    
}
void ConfigureADC(void)
{
    EALLOW;

    //write configurations
    AdcaRegs.ADCCTL2.bit.PRESCALE = 0; //set ADCCLK divider to /1

    AdcSetMode(ADC_ADCA, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);


    //Set pulse positions to late
    AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;


    //power up the ADCs
    AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;

    DELAY_US(1000);
    EDIS;
}

Can anyone has an idea about reason of this?

  • When i change trigger channel from timer0 to ePWM , there is not any changing about reading...the issue is still..
  • Hi Eren,

    Check if the acquisition prescale(ACQPS) value is correctly set. Also, let me know the rate at which ADC is triggered.

    Thanks
    Vasudha
  • Thank you Vasudha for answer.
    i have tried many different prescale but none of them worked.i have set CPU timer for 10uS and in this time i set Adca(4 channel),Adcb(4 channel), and Adcd(4 channel)...but i chanced This time 10uS to 100uS too but Nothing changed.
  • Now as 9.3.2 section in spruhx5e, i have update my Rs to 250Ohm,

    Acording to this,

    chosed 1/4LSB

    t=-ln(0.25/4096)*(250+300)*14.5pF

    =77nS

    My system clock is 200MHz So 1/SYCLK=5nS

    from here

    ACQPS=14.4 chosed 15..

    when i used this configuration my ADCA0 reads true value, BUT, Although there is not any analog signal on ADCA1, ADCA1 reads some values.!!!!

    what can i do for this?

  • By the way i am a little bit confused when i read more about this :)..

    section 9.2 in spruhx5e there is a text which is:

    """""the S+H duration is the value of the ACQPS field of the SOC being converted, plus one, times the

    SYSCLK period. The user must ensure that this duration exceeds both 1 ADCCLK period and the

    minimum S+H duration specified in the datasheet. The conversion time is approximately 10.5 ADCCLK

    cycles in 12-bit mode and 29.5 ADCCLK cycles in 16-bit mode. The exact conversion time is always a

    whole number of SYSCLK cycles.""""

    As you see the convertion time apprx. 10.5 ADCCLK, when you set divider to 1 ,every adc clock is 20nS so 20nS*10.5=210nS is convertion time for calculation ACQPS is about 44  (220nS/5nS), but in CCS examples ACQPS is take 14, how it could be!!!!!..

  • Hi All,

    There is not anyone who do not have an idea aout this issue??

  • Hi Eren,

    The ACQPS and conversion time are different values. PFB the description from device TRM.

    The process of converting an analog voltage to a digital value is broken down into an S+H phase and a
    conversion phase. The ADC sample and hold circuits (S+H) are clocked by SYSCLK while the ADC
    conversion process is clocked by ADCCLK. ADCCLK is generated by dividing down SYSCLK based on
    the PRESCALE field in the ADCCTL2 register.

    The S+H duration is the value of the ACQPS field of the SOC being converted, plus one, times the
    SYSCLK period. The user must ensure that this duration exceeds both 1 ADCCLK period and the
    minimum S+H duration specified in the datasheet. The conversion time is approximately 10.5 ADCCLK
    cycles in 12-bit mode and 29.5 ADCCLK cycles in 16-bit mode. The exact conversion time is always a
    whole number of SYSCLK cycles.

    Thanks
    Vasudha