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TMS320F28375S: internal ADC signals - minimum acquisition time (Tsh)

Lenio Cacula
Genius 16820 points
Part Number: TMS320F28375S


When sampling internal ADC signals, what is the absolute minimum time for ACQPS? I understand the sample window has to be at least 1 ADCCLK and that the minimum sample duration is 320ns for 16 bits and 75 ns for 12 bits; my question is whether I should consider anything else beyond the constraints I just listed.

Thank you!

  • 0
    TI__Guru 60865 points

    Hi Lenio,

    Connections to the opens-shorts circuit go through a defined impedance, so you can pretty easily calculate the projected S+H duration.

    Output of the buffered DAC via internal channels should be pretty strong, but there generally won't be much capacitance on the output pin (max capacitive load is 100pF).  You might want a longer S+H in this case since sampling will cause a step on the voltage on the DAC output (due to inrush current into the ADC sampling capacitor) and then the DAC will have to settle the output.  

    Internal VREFLO connections should allow a generally short S+H time, but again there isn't much capacitance on the input to act as a 'flywheel capacitance', so you might want to allow a little extra time.  

    Not sure if there are other internal connections I'm missing?