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TMS320F28068M: Trying to understand example external_interupt

Part Number: TMS320F28068M
In example C:\ti\c2000\C2000Ware_1_00_06_00\device_support\f2806x\examples\c28\external_interrupt

There is a part where they "connect XINT1 and XINT2 to Group 1 with interrupt 4 and 5". As there are 96 interrupts sources available I understand that these should be MUXed to the 12 available cpu interrupts.
And each cpu interrupt is a "Group" of eight interrupts. But how are XINT1 and XINT2 connected to Group 1 INT4 and INT5(they are just enabled)? And why are the XINT1 and XINT PieVectTables directly connected to the interrupt functions?
I cannot completely follow the story with the corresponding code? Some code seems to be missing in the example to really make it sense?Thank you in advance.

 EALLOW;	// This is needed to write to EALLOW protected registers
    PieVectTable.XINT1 = &xint1_isr;
    PieVectTable.XINT2 = &xint2_isr;
    EDIS;   // This is needed to disable write to EALLOW protected registers

    //
    // Enable XINT1 and XINT2 in the PIE: Group 1 interrupt 4 & 5
    // Enable INT1 which is connected to WAKEINT
    //
    PieCtrlRegs.PIECTRL.bit.ENPIE = 1;          // Enable the PIE block
    PieCtrlRegs.PIEIER1.bit.INTx4 = 1;          // Enable PIE Group 1 INT4
    PieCtrlRegs.PIEIER1.bit.INTx5 = 1;          // Enable PIE Group 1 INT5
    IER |= M_INT1;                              // Enable CPU INT1
    EINT;          

  • I think you have understood correctly and the code is correct.

    On C28x, the interrupt sources are hard-wired to specific PIE interrupts. For F2806x, interrupts from XINT1 and XINT2 come in on PIE group 1; at INT1.4 and INT1.5 respectively. These lines are enabling the interrupts at the PIE level:

    PieCtrlRegs.PIEIER1.bit.INTx4 = 1;
    PieCtrlRegs.PIEIER1.bit.INTx5 = 1;

    ...then this line enables the core level interrupt:
    IER |= M_INT1;

    ...and this is enabling the global interrupt mask:
    EINT;

    When an interrupt is taken by the core, the PC branches to an address contained in the PIE vector table in RAM. This table is loaded with addresses from the "PieVectTable" structure; and the ISR addresses for these two interrupts are being loaded in the lines:

    PieVectTable.XINT1 = &xint1_isr;
    PieVectTable.XINT2 = &xint2_isr;

    The structure is in the file F2806x_PieVect.h, and it gets loaded with default addresses during device configuration. The two lines above are over-writing the default addresses with those of the user ISRs.

    This is all you need to do to configure the XINT interrupts on this device. The attached slides are taken from the multi-day workshop for the F2806x and may help.

    Regards,

    Richard

    C28xm04.pdf