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Original question:

TMS320F28374D: RAM parity check on address error sequence

TMS320F28375S: Calculating the RAM data and address parity

Jordan Nelson
Prodigy 250 points
Part Number: TMS320F28375S

What is the Parity scheme for the TMS320F2837xS chips in the GSx and LSx RAM sectors? Based on testing it seems the parity for the data value is always stored as even parity. However for the address parity it seems to be different per RAM sector, example shown below:

RAM Sector

Address

Number of 1’s

Parity Bit Value

Parity Type

LS0

0x877E

10

1

ODD

LS1

0x8F8E

9

1

EVEN


Can TI please provide the parity that each RAM block uses and scheme?

In gathering this data we used a Launchpad with the TMS320F28375S to access the registers described in the TRM (SPRUHX5F) section 3.11.1.8.  For an example of RAM data and address parity tests, I looked into the SafeTI Diagnostic Library however there is no such test on the address parity.

  • 0
    TI__Genius 17849 points

    Jordan,

    You can find more information about the parity regarding LSx adn GSx on page 184 of the datasheet. http://www.ti.com/lit/ds/symlink/tms320f28375s.pdf

    Regards,

    Ozino

  • 0 in reply to Ozino Odharo
    TI__Mastermind 32995 points

    Hi,

    I will check with another engineer to confirm.

    sal

  • 0 in reply to Sal Pezzino
    Prodigy 250 points

    Hey Sal,

    Table 3-13 of the TRM (SPRUHX5F) defines that bit 16 of the memory will contain the parity for the address and it can be modified when LSxTEST.TEST_LSy is set to 0b10 (where y=0-5) and GSxTEST.TEST_GSy is set to 0b10 (where y=0-15).  It does seem that there is some correlation between what we observe at bit 16 and the address in the RAM.

    In section 3.11.1.7 of the TRM it states that the parity scheme is even, but we are finding some instances of odd parity in the address.

    Thanks,

    -Jordan 

  • 0 in reply to Jordan Nelson
    TI__Mastermind 32995 points

    Hi Jordan,

    We are checking with design and will reply back here.

    sal

  • 0 in reply to Sal Pezzino
    TI__Guru** 113775 points

    Hi,

    The address parity is calculated for 32bit address and for offset only (not the base address).

    For following two case -


    1) Since it's 4KB RAM block, only 11bits of address (which represents the offset) need to be considered for parity calculation.

    2) Also discard the LSB bit for parity calculation.

    0x877E -> 77E -> 9 1's

    0x8F8E -> 78E -> 7 1's

    Hence parity value is same for both the address.

    Hope this is clear. I am going to raise a request to add this clarification in documentation.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Prodigy 250 points

    Hey Vivek,

    Thanks for the clarification, we would like to see this as an update to the documentation in support of our design.

    Can you confirm that the bit mask then for the address to calculate the parity is 0x7FE?

    Thanks again,

    -Jordan

  • 0 in reply to Jordan Nelson
    TI__Guru** 113775 points

    HI Jordan,

    Can you confirm that the bit mask then for the address to calculate the parity is 0x7FE?

    Yes, for 4KB RAM block, this is correct mask value. This will change based on the size of RAM block. E.g. for 8KB RAM block, this mask value will be 0xFFE

    Regards,

    Vivek Singh