CCS/TMS320F28379D: Offset in phase shift

Tool/software: Code Composer Studio

hello,

I am operating ePWm 1 and ePWM 2 module at same frequency and zero phase shift between them by making the TBPHS register=0. However I am observing a finite phase shift offset on my scope. below is the code snippet for the same. Please point out if there is any mistake in the code. Thank you

void InitEPwm1Example()
{

//
// Setup TBCLK
//
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
EPwm1Regs.TBPRD = switching_period; // Set timer period
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm2Regs.TBPHS.bit.TBPHSHR = 0; // Phase is 0
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync down stream module
EPwm1Regs.TBCTR = 0x0000; // Clear counter
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

//
// Setup shadow register load on ZERO
//
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

//
// Set Compare values
//
EPwm1Regs.CMPA.bit.CMPA = duty; // Set compare A value
EPwm1Regs.CMPB.bit.CMPB = duty; // Set Compare B value

//
// Set actions
//
EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // Set PWM1A on Zero
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM1A on event A,
// up count

//
// Set dead band
//
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBCTL.bit.HALFCYCLE = 1;
EPwm1Regs.DBRED.bit.DBRED = 1;
EPwm1Regs.DBFED.bit.DBFED = 1;

EALLOW; // Note these registers are protected
// and act on both chA and chB
EPwm1Regs.HRCNFG.all = 0x0; // clear all bits first
EPwm1Regs.HRCNFG.bit.EDGMODE = HR_BEP; // Control Both Edge Position A
EPwm1Regs.HRCNFG.bit.EDGMODEB = HR_BEP; // Control Both Edge Position B
EPwm1Regs.HRCNFG.bit.CTLMODE = HR_PHS; // PHSHR controls the MEP A
EPwm1Regs.HRCNFG.bit.CTLMODEB = HR_PHS; // PHSHR controls the MEP B
EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; // Shadow load on CTR=Zero for A
EPwm1Regs.HRCNFG.bit.HRLOADB = HR_CTR_ZERO; // Shadow load on CTR=Zero for B
EDIS;
}

//
// InitEPwm2Example - Initialize EPWM2 values
//
void InitEPwm2Example()
{

//
// Setup TBCLK
//
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
EPwm2Regs.TBPRD = switching_period; // Set timer period
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm2Regs.TBPHS.bit.TBPHS =0; // Phase is 0
EPwm2Regs.TBPHS.bit.TBPHSHR = 000; // Phase is 0
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Sync down stream module
EPwm2Regs.TBCTR = 0x0000; // Clear counter
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;

//
// Setup shadow register load on ZERO
//
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

//
// Set Compare values
//
EPwm2Regs.CMPA.bit.CMPA = duty; // Set compare A value
EPwm2Regs.CMPB.bit.CMPB = duty; // Set Compare B value

//
// Set actions
//
EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET; // Set PWM2A on Zero
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM2A on event A,
// up count

//
// Set dead band
//
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm2Regs.DBCTL.bit.HALFCYCLE = 1;
EPwm2Regs.DBRED.bit.DBRED = 2;
EPwm2Regs.DBFED.bit.DBFED = 2;

EALLOW; // Note these registers are protected
// and act on both chA and chB
EPwm2Regs.HRCNFG.all = 0x0; // clear all bits first
EPwm2Regs.HRCNFG.bit.EDGMODE = HR_BEP; // Control Both Edge Position A
EPwm2Regs.HRCNFG.bit.EDGMODEB = HR_BEP; // Control Both Edge Position B
EPwm2Regs.HRCNFG.bit.CTLMODE = HR_PHS; // PHSHR controls the MEP A
EPwm2Regs.HRCNFG.bit.CTLMODEB = HR_PHS; // PHSHR controls the MEP B
EPwm2Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; // Shadow load on CTR=Zero for A
EPwm2Regs.HRCNFG.bit.HRLOADB = HR_CTR_ZERO; // Shadow load on CTR=Zero for B
EDIS;

}