TMS320F28035: 28035 i2c interrupt

Hi Sagar,

Can you further explain the below? Are you saying the trigger depends on the state of the read/write bit after the slave address (8th bit)?

sagar shah54 said:

It Does trigger when I have i2c Write (as a slave ) but does not work during read time.

If possible, providing waveform screenshots of the working and not-working case would be helpful in understanding the issue.

Best,

Kevin

So My Question is-

1)When I send data from 28379(master) to Slave 28035 as write i2c isr in 28035 gets triggered and I read from I2caRegs.I2CDRR in ISR and the operation completes successfully.

2) when I do the same but 28379 wants to read from slave 28035 - i2ca ISR in 23035 does not get triggered on AAS. I have AAS bit enabled in i2cier reg.

So the clock gets low. but if I poll AAS bit then the transaction is done successfully. So why is the i2c interrupt in 28035 not getting triggered even though enabled for AAS bit?

I attached a screenshot of registers when it is hab=nged. So let me know if I did something incorrectly.

Thanks, 

Kevin, Do you still need more data?

Hi Sagar,

Sorry for the delay in my response. Does this still occur if you perform a read operation initially instead of a write operation?

The I2CISRC.bit.INTCODE is showing a value of 0x6, which is a STOP condition interrupt. Maybe this interrupt hasn't been cleared/serviced in time for the AAS interrupt to be detected. I believe the clearing methods from the below I2CSTR.SCD bit description should work:

Best,

Kevin

Yes, I have made several changes while waiting for your reply. If you can reply faster it would be a great help.

I have only two interrupt enabled.

I2caRegs.I2CIER.all = 0x0;

I2caRegs.I2CIER.bit.RRDY = 1;

I2caRegs.I2CIER.bit.XRDY = 1;

So Still it does not interrupt when intended.

Also Why the interrupt triggers when 2CISRC.bit.INTCODE = 0?

Also if I put a delay 150 microseconds at the beginning of i2c isr then all my operations work smoothly.

So can you help what would be the problem as to why I need a Delay.

Thanks.

Sadar,

sagar shah54 said:

I have only two interrupt enabled.

I2caRegs.I2CIER.all = 0x0;

I2caRegs.I2CIER.bit.RRDY = 1;

I2caRegs.I2CIER.bit.XRDY = 1;

These interrupts are not intended to be used and may not trigger when using I2C FIFO mode.

sagar shah54 said:

Also Why the interrupt triggers when 2CISRC.bit.INTCODE = 0?

How have you tested this? The INTCODE should have the respective interrupt value when read by the CPU. Maybe something is clearing it based on what you're seeing.

sagar shah54 said:

Also if I put a delay 150 microseconds at the beginning of i2c isr then all my operations work smoothly.

So can you help what would be the problem as to why I need a Delay.

Can you please share a code snippet of your ISR that includes this delay?

Best,

Kevin

__interrupt void i2c_int1a_isr(void)     // I2C-A
{
//
int j;
intcode = I2caRegs.I2CISRC.bit.INTCODE;
 if(intcode != 0){
       
        DELAY_US(130); // This is the delay which makes it work 

        if(I2caRegs.I2CSTR.bit.SDIR == 1 && intcode == 5){ // Write to 28379 to Dual Core
          I2caRegs.I2CDXR = dataRx[0];
          while(I2caRegs.I2CSTR.bit.XRDY != 1) {}; // 1 = Data transferred tp the core TX register after shifting data
		  
		  I2caRegs.I2CDXR = dataRx[1];
          while(I2caRegs.I2CSTR.bit.XRDY != 1) {}; // 1 = Data transferred tp the core TX register after shifting data
		  
		  I2caRegs.I2CDXR = dataRx[2];
		   while(I2caRegs.I2CSTR.bit.XRDY != 1) {};// 1 = Data transferred tp the core TX register after shifting data
		  
		  I2caRegs.I2CDXR = dataRx[3];
		  while(I2caRegs.I2CSTR.bit.XRDY != 1) {}; // 1 = Data transferred tp the core TX register after shifting data

        }

        if(I2caRegs.I2CSTR.bit.SDIR == 0 && intcode == 4){ //read from 28379 and save Register
            while(I2caRegs.I2CFFRX.bit.RXFFST < 4)  {};
             
			  // wait for 4 byte data to arrive
            
                for(j =0 ;j < 4; j++){
                    dataRx[j] = I2caRegs.I2CDRR;
                }
        
        } // END OF CASE INT = 4

  } // END OF INTCODE != 0

    PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;
}

I am not using FIFO mode I am using Cnt = 4 bytes. Also when I put a breakpoint in ISR I have an interrupt code to be 0 sometimes.

there is a delay required is shown in ISR code. Let me know if you need anything and hope I can understand this quickly if possible.

Thanks,

Sagar