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CCS/TMS320F28069: TMS320F28069 ADC issues

WANG NING
Intellectual 490 points
Part Number: TMS320F28069

Tool/software: Code Composer Studio

I have been developing data acquisition hardware based on 28069 MCU and found some issues with 12bit ADC, wondering if someone can explain.

My ADC configure: 

AdcRegs.ADCCTL2.bit.ADCNONOVERLAP = 1; // Enable non-overlap mode
AdcRegs.ADCCTL1.bit.INTPULSEPOS = 1; // late interrupt pulse
AdcRegs.INTSEL1N2.bit.INT1E = 1; // Enabled ADCINT1
AdcRegs.INTSEL1N2.bit.INT1CONT = 1; // Enable ADCINT1 Continuous mode
AdcRegs.INTSEL1N2.bit.INT2E = 1; // Enabled ADCINT2
AdcRegs.INTSEL1N2.bit.INT2CONT = 1; // Enable ADCINT2 Continuous mode
AdcRegs.INTSEL1N2.bit.INT1SEL = 0; // setup EOC0 to trigger ADCINT1 to fire
AdcRegs.INTSEL1N2.bit.INT2SEL = 1; // setup EOC1 to trigger ADCINT2 to fire
AdcRegs.ADCSOC0CTL.bit.CHSEL = 0; // set SOC0 channel select to ADCINA0
AdcRegs.ADCSOC1CTL.bit.CHSEL = 8; // set SOC1 channel select to ADCINB0
AdcRegs.ADCSOC0CTL.bit.TRIGSEL = 0; // set SOC0 start trigger on cputimer1,but initially off
AdcRegs.ADCSOC1CTL.bit.TRIGSEL = 0; // set SOC1 start trigger on cputimer1,but initially off
AdcRegs.ADCINTSOCSEL1.all = 0x0;
AdcRegs.ADCINTSOCSEL2.all = 0x0;
AdcRegs.ADCSOC0CTL.bit.ACQPS = 8; // set SOC0 S/H Window to 9 ADC Clock Cycles,
AdcRegs.ADCSOC1CTL.bit.ACQPS = 8;

1. different SR gives slightly different ADC result.
    Giving input at about half Vref, I had a sweep of different SR (100KHz to 3MHz). Some SR gives 3-4 LSB difference against normal 12bit code. Not sure if it is normal?

2. At higher SR ( such as 1.5MHz), I have to use OVERLAP for both channel on, in this case, channel A and B will affect each other. e.g. If I turn on or off one of the channel, ADC result of the other channel can be noticeable higher or lower. So I have to use NONOVERLAP, and ACQPS >7 to eliminate this, resulting lower SR.

3. When I am measuring small signal, I can observe at least 3-4LSB of ADC result is not correct. for example, I supply ADCIN with 50mV 1KHz sine signal centering at 1024mV(Vref=2048mV), whenever the signal cross the mid-value which is about 1024mV, the result waveform is like oscillating a bit (at least 3-4 LSB) rather than smooth waveform and then becomes normal.

4. Setting ACQPS=6 or 7 is not working for SR = 2MHz, the result waveform becomes rather bad, huge distortion. but it is OK for other sample rate, even for higher SR=3MHz. So I set ACQPS=8, and it is fine.

Are these known issues with the ADC? or is it caused by maybe bad layout? Or my ADC configure is not correct?

Very appreciate if someone can give me some clue.

  • 0
    TI__Guru 62975 points

    WANG NING said:
    1. different SR gives slightly different ADC result. 

        Giving input at about half Vref, I had a sweep of different SR (100KHz to 3MHz). Some SR gives 3-4 LSB difference against normal 12bit code. Not sure if it is normal?

    This is not out of the ordinary. Different operating conditions should be expected to produce small variations in results. The overall performance is expected to satisfy datasheet specifications.

    WANG NING said:
    2. At higher SR ( such as 1.5MHz), I have to use OVERLAP for both channel on, in this case, channel A and B will affect each other. e.g. If I turn on or off one of the channel, ADC result of the other channel can be noticeable higher or lower. So I have to use NONOVERLAP, and ACQPS >7 to eliminate this, resulting lower SR.

    3. When I am measuring small signal, I can observe at least 3-4LSB of ADC result is not correct. for example, I supply ADCIN with 50mV 1KHz sine signal centering at 1024mV(Vref=2048mV), whenever the signal cross the mid-value which is about 1024mV, the result waveform is like oscillating a bit (at least 3-4 LSB) rather than smooth waveform and then becomes normal.

    4. Setting ACQPS=6 or 7 is not working for SR = 2MHz, the result waveform becomes rather bad, huge distortion. but it is OK for other sample rate, even for higher SR=3MHz. So I set ACQPS=8, and it is fine.

    Make sure that your input signal is conditioned properly (for example with a buffer) so that it can fully charge the S/H capacitor within the ACQPS window.  From the datasheet:

    You can also review the errata for known issues.

  • 0 in reply to tlee
    Intellectual 490 points

    I have a RC between the ADCIN and opamp buffer for band limiting. R=50 Ohms, C=10 nF. Do you think this is the cause?

  • 0 in reply to WANG NING
    TI__Guru 62975 points

    WANG NING,

    The RC cut-off is likely contributing to the issue.  You will need to match the RC cut-off to the bandwidth required to charge the S/H capacitor within the ACQPS window.

    Note that there is only one S/H capacitor per group (A and B) of ADC channels so the starting voltage of the S/H capacitor is directly related to the value of the most recent conversion for that group.

    -Tommy

  • 0 in reply to tlee
    Intellectual 490 points

    so,  RC = 50 Ohm*10nF = 0.5us, while ACQPS window = 10*(1/45MHz) = 0.2us. RC Tau should be significantly smaller than ACQPS window

    Is my understanding correct?  If so, I should put the RC filter before the buffer.

    Ning

  • 0 in reply to WANG NING
    TI__Guru 62975 points

    Ning,

    Correct, placing the RC filter at the input of the buffer should provide you with a faster settling time assuming that your buffer has sufficient bandwidth to respond to the S/H charging profile.

    If the buffer cannot keep up with the ACQPS window, you can also consider changing your RC values so that the capacitor is able to quickly provide most of the needed charge to the S/H capacitor of the ADC.  The buffer would be responsible for slowly recharging the large capacitor between samples.  A good starting point to try would be ~47nF.

    -Tommy

  • 0 in reply to tlee
    Intellectual 490 points

    tlee said:

    Ning,

    Correct, placing the RC filter at the input of the buffer should provide you with a faster settling time assuming that your buffer has sufficient bandwidth to respond to the S/H charging profile.

    If the buffer cannot keep up with the ACQPS window, you can also consider changing your RC values so that the capacitor is able to quickly provide most of the needed charge to the S/H capacitor of the ADC.  The buffer would be responsible for slowly recharging the large capacitor between samples.  A good starting point to try would be ~47nF.

    -Tommy

    one more question:

    if I modify ADC registers during ADC running, will this be a problem?

    I have observed that changing NONOVERLAP bit will cause ADC stop working, no data put in result register. So I have to stop epwm SOC before updating this bit, then restart epwm counting, then it works fine. 

    Is it necessary to reset ADC to update ADC config? As I can see data changed a bit, if I either change sample rate or turn on/off one the channel.

  • 0 in reply to tlee
    Intellectual 490 points

    one more question:

    if I modify ADC registers during ADC running, will this be a problem?

    I have observed that changing NONOVERLAP bit will cause ADC stop working, no data put in result register. So I have to stop epwm SOC before updating this bit, then restart epwm counting, then it works fine. 

    Is it necessary to reset ADC to update ADC config? As I can see data changed a bit, if I either change sample rate or turn on/off one the channel.

  • 0 in reply to WANG NING
    TI__Guru 62975 points

    Ning,

    You should avoid changing global ADC settings while the converter is active.  As you have found, the easiest way to do this is to disable the ADC trigger and update the settings while the ADC is idle.  A reset will not be necessary.

    SOCs can be updated when there is no pending trigger for the SOC being modified.

    -Tommy