This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28377S: Up-Down PWM with phase control - result is oposite to expetations

Part Number: TMS320F28377S

Hello,

I'm implementing 3-Phase PMSM. Everything is already nice configured except the phase shift.

There is absolute zero phase shift expected.

Initialy I set the same PWM 50% for all ePWMs.

With TBPHS == 0 for slave ePWMs I get 20ns delay (slave goes high later as master) what is already documented in TRM.

With any value, e.g. TBPHS == 2 the slave goes high 40ns later. The bigger the TBPHS for slave the bigger is the phase shift.

But I have to shift the slave in opposite direction.

EPwm1Regs EPWM Registers
TBCTL 0x0012 Time Base Control Register [Memory Mapped]
FREE_SOFT 00 Emulation Mode Bits
PHSDIR 0 Phase Direction Bit
CLKDIV 000 Time Base Clock Pre-scaler
HSPCLKDIV 000 High Speed TBCLK Pre-scaler
SWFSYNC 0 Software Force Sync Pulse
SYNCOSEL 01 Sync Output Select
PRDLD 0 Active Period Load
PHSEN 0 Phase Load Enable
CTRMODE 10 Counter Mode
TBPHS 0x00000000 Time Base Phase High [Memory Mapped]
TBPHS 0000000000000000 Phase Offset Register
TBPHSHR 0000000000000000 Extension Register for HRPWM Phase (8-bits)
TBPRD 0x0C35 Time Base Period Register   [Memory Mapped]
TBPRD 3125 (Decimal) Time base period register
CMPA 0x00000000 Counter Compare A Register   [Memory Mapped]
CMPB 0x061A0000 Compare B Register   [Memory Mapped]
CMPB 0000011000011010 Compare B Register
CMPBHR 0000000000000000 Compare B High Resolution Bits
EPwm2Regs EPWM Registers
TBCTL 0x0006 Time Base Control Register [Memory Mapped]
FREE_SOFT 00 Emulation Mode Bits
PHSDIR 0 Phase Direction Bit
CLKDIV 000 Time Base Clock Pre-scaler
HSPCLKDIV 000 High Speed TBCLK Pre-scaler
SWFSYNC 0 Software Force Sync Pulse
SYNCOSEL 00 Sync Output Select
PRDLD 0 Active Period Load
PHSEN 1 Phase Load Enable
CTRMODE 10 Counter Mode
TBPHS 0x00020000 Time Base Phase High [Memory Mapped]
TBPHS 0000000000000010 Phase Offset Register
TBPHSHR 0000000000000000 Extension Register for HRPWM Phase (8-bits)
TBPRD 0x0C35 Time Base Period Register   [Memory Mapped]
TBPRD 3125 (Decimal) Time base period register
CMPA 0x0C2F0000 Counter Compare A Register   [Memory Mapped]
CMPB 0x061A0000 Compare B Register   [Memory Mapped]
CMPB 1562 (Decimal) Compare B Register
CMPBHR 0000000000000000 Compare B High Resolution Bits
  • Hi,

    Your understanding is correct, you need to use TBPHS == 2.
    Quickly looking over your configuration, you may want to use PHSDIR=1, because you want the counter to count up after loading the phase.
    This also explains why you are seeing the phase shift increase with increasing TBPHS.
    Please try setting PHSDIR and let me know your observation.