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TMS320F28377S: TMS320F28377S

ysn
Prodigy 200 points

Part Number: TMS320F28377S

Hi,

I am trying enable External Interrupts on TMS320F28377S device with following GPIOs

1. XINT1 -- > GPIO66

1. XINT2 -- > GPIO67

1. XINT3 -- > GPIO68

I have initialized all three interrupts in same way. The XINT1 and XINT2 are working fine but unable to bringup XINT3 associated with GPIO68. I have also verified GPIO68 with XINT2 and is working fine.

Hence there is no issue with HW or GPIO68 mapping. I configured all three interrupts under GROUP 1 IER. 

Kindly Resolve the issue ASAP

  • 0
    TI__Guru** 116971 points

    Hi,

    XINT3 is mapped on 12.1 in PIE (different than XINT1/XINT2). Please see if you are configuring that correctly.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Prodigy 200 points

    Hi Vivek Singh,

    Thanks for quick reply.

    I am using below configuration in my init function 

    EALLOW; // This is needed to write to EALLOW protected registers
    PieVectTable.XINT1_INT = &xint1_isr;
    PieVectTable.XINT2_INT = &xint2_isr;
    PieVectTable.XINT3_INT = &xint3_isr;
    EDIS; // This is needed to disable write to EALLOW protected registe

    PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block
    PieCtrlRegs.PIEIER1.bit.INTx4 = 1; // Enable PIE Group 1 INT4
    PieCtrlRegs.PIEIER1.bit.INTx5 = 1; // Enable PIE Group 1 INT5
    PieCtrlRegs.PIEIER12.bit.INTx1 = 1; // Enable PIE Group 1 INT5

    IER |= M_INT1;
    IER |= M_INT12;

    EALLOW;
    GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 0; // GPIO
    GpioCtrlRegs.GPCDIR.bit.GPIO66 = 0; // input
    GpioCtrlRegs.GPCQSEL1.bit.GPIO66 = 0; // XINT1 Synch to SYSCLKOUT only

    GpioCtrlRegs.GPCMUX1.bit.GPIO67 = 0; // GPIO
    GpioCtrlRegs.GPCDIR.bit.GPIO67 = 0; // input
    GpioCtrlRegs.GPCQSEL1.bit.GPIO67 = 0; // XINT2 Synch to SYSCLKOUT only

    GpioCtrlRegs.GPCMUX1.bit.GPIO68 = 0; // GPIO
    GpioCtrlRegs.GPCDIR.bit.GPIO68 = 0; // input
    GpioCtrlRegs.GPCQSEL1.bit.GPIO68 = 0; // XINT3 Synch to SYSCLKOUT only
    EDIS;

    GPIO_SetupXINT1Gpio(66);
    GPIO_SetupXINT2Gpio(67);
    GPIO_SetupXINT3Gpio(68);


    XintRegs.XINT1CR.bit.POLARITY = 0; // Falling edge interrupt
    XintRegs.XINT2CR.bit.POLARITY = 0; // Falling edge interrupt
    XintRegs.XINT3CR.bit.POLARITY = 0; // Falling edge interrupt

    XintRegs.XINT1CR.bit.ENABLE = 1; // Enable XINT1
    XintRegs.XINT2CR.bit.ENABLE = 1; // Enable XINT2
    XintRegs.XINT3CR.bit.ENABLE = 1; // Enable XINT3

     

    Kindly Review and and let me know if any issue.

     

    Regards,

    Stalin 

  • 0 in reply to ysn
    TI__Guru** 116971 points

    Stalin,

    This code looks good. Can you set a breakpoint at "XintRegs.XINT1CR.bit.POLARITY = 0; // Falling edge interrupt" and check the configuration in  "INPUT6SELECT" (XINT3 is mapped on INPUT6 of INPUTXBAR) register in CCS register view.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Prodigy 200 points

    Hi Vivek Singh,

    Thanks for your inputs. BTW, We have solved XINT3 issue. Apart from above initialization we have to also configure 

     GpioCtrlRegs.GPCGMUX1.bit.GPIO68 = 0;         // GPIO.

    I don't really understood the reason but both CGMUX and CMUX have to be configured especially for XINT3 interrupt. 

    Regards,

    Stalin  

  • 0 in reply to ysn
    TI__Guru** 116971 points

    Stalin,

    Good to know you were able to find the issue. It's strange though because be default values of that filed should be '0' unless you have changed it in your code somewhere. Can you check the value of this bit via CCS register view before you are setting it to '0' in your code?

    Regards,

    Vivek Singh