TMS320F28335: Problem about McBSP

F.F

Part Number: TMS320F28335

Dear team:

I have some problem about McBSP configuration.
In the loop-back mode, MCBSP communication can communicate normally and receive data. But after turn off the loop-back mode (McbspaRegs.SPCR1.bit.DLB = 0;) and communicate between two boards, The receiving board can enter the receiving interrupt, but the value of the receiving register is always 0. The pin connection was checked and no problem was found. Looking at the sending pin with an oscilloscope, the clock, frame synchronization signal and data are all available, but the data can not be received.

Below is my program (Only modified McbspaRegs.SPCR1.bit.DLB = 0;):

void InitMcbspa(void)
{
// McBSP-A register settings

McbspaRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter
McbspaRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word
McbspaRegs.SPCR1.bit.DLB = 1; // Enable loopback mode for test. Comment out for normal McBSP transfer mode.

McbspaRegs.MFFINT.all=0x0; // Disable all interrupts
McbspaRegs.RCR1.all=0x0;
McbspaRegs.RCR2.all=0x05;
// McbspaRegs.RCR1.all=0x0; // Single-phase frame, 1 word/frame, No companding (Receive)
// McbspaRegs.RCR1.bit.RFRLEN1=4;

McbspaRegs.XCR1.all=0x0;
McbspaRegs.XCR2.all=0x05;

// Single-phase frame, 1 word/frame, No companding (Transmit)
// McbspaRegs.XCR1.bit.XFRLEN1=4;

McbspaRegs.PCR.bit.FSXM = 1; // FSX generated internally, FSR derived from an external source
McbspaRegs.PCR.bit.CLKXM = 1; // CLKX generated internally, CLKR derived from an external source
McbspaRegs.SRGR1.all = 0xff04; //
McbspaRegs.SRGR2.all = 0xA000; //
// McbspaRegs.SRGR2.bit.CLKSM = 1; // CLKSM=1 (If SCLKME=0, i/p clock to SRG is LSPCLK)
//McbspaRegs.SRGR2.bit.FPER = 31; // FPER = 32 CLKG periods

//McbspaRegs.SRGR1.bit.FWID = 0; // Frame Width = 1 CLKG period
// McbspaRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL;// CLKG frequency = LSPCLK/(CLKGDV+1)
McbspaRegs.MFFINT.bit.RINT = 1;

delay_loop(); // Wait at least 2 SRG clock cycles

McbspaRegs.SPCR2.bit.GRST=1;
McbspaRegs.SPCR1.bit.RINTM=0; //中断由RRDY产生// Enable the sample rate generator
clkg_delay_loop(); // Wait at least 2 CLKG cycles
McbspaRegs.SPCR2.bit.XRST=1; // Release TX from Reset
McbspaRegs.SPCR1.bit.RRST=1; // Release RX from Reset
McbspaRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset

}