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LAUNCHXL-F28379D: SCI communication between cpus

Christian Curll
Prodigy 160 points
Part Number: LAUNCHXL-F28379D


I am trying to use two SCIs(B and C) to send data between the two CPUs on the LaunchXL.  As far as I can tell I have set everything up correctly using a similar setup to that of SCIA for usb communication.  When debugging I can see the TX bits of each SCI set but when trying to read data in from CPU1 to CPU2 (SCIBRXD TO SCICTXD) the RXFFST flag is not being set when debugging on a single CPU SCIC SAR is filled with the proper data but I cannot store that data on CPU2 using this method:

while(done == 1){
        while(ScicRegs.SCIFFRX.bit.RXFFST == 0x0) {}    //wait for RX buf to not be empty
            if(ScicRegs.SCIRXBUF.bit.SAR == 0x3F)//finish transmission on receiving a ?
                {
                done = 0;
                }
            ReceivedChar[i] = ScicRegs.SCIRXBUF.bit.SAR; //receive a character from RXBUF to ReceivedChar pointer array
            ScicRegs.SCITXBUF.all = ReceivedChar[i]; //transmit the ReceivedChar character back to CPU1
            ScicRegs.SCIRXBUF.bit.SAR &= 0x00;  //clear RX buf for next character to be ReceivedChar
            ScicRegs.SCITXBUF.bit.TXDT &= 0x0000;  //clear TX buf for next character to be ReceivedChar
            i++;//iterative tracker to find how many chars are sent and store data in order
    }//end of while done = 1
This code is used to get data from a serial transmission from the PC on CPU1 with SCIA but will not do the same to receive data from CPU1 with SCIC
this code will sit and wait at the loop containing the RX flag but never continue even when data is being sent to the SAR I am using 9600 baud n=8 no parity.
I know this is a roundabout way to code this but I am interested in getting it to work in this manner, I can upload my setup methods if need be but any insight is appreciated
  • 0
    TI__Genius 17315 points

    Christian,

    As you probably know, the SCIs by default are assigned to CPU1.  For an SCI to be assigned to either CPU1 or CPU2, you will need to configure the CPUSEL5 register.  It is important to note that this register must be configured prior to enabling the peripheral clocks.  That is, the clock multiplexer controlled by this register is not glitch-free.  Therefore the CPUSELx register must be configured before the PCLKCRx register.  Next, as a test and to keep it simple, you might want to confirm each SCI is operating properly by using only CPU1.  Once you confirm it is working you can then assign it to CPU2. Be sure that the SCI GPIOs are configured correctly. Also, remember when using the SCI FIFOs you must have the SCI FIFO enhancements enabled (SCIFFENA) in the SCIFFTX register.

    I hope this helps. If this answers your question, please click the green "Verified Answer" button.

    - Ken

  • 0 in reply to Ken Schachter
    Prodigy 160 points

    So if I understand what you said, when the PCLKCRx reg is assigned in InitSysCtrl(), it can cause glitches later down the line when I try to give peripheral control to CPU2.  What portions of the init do I have to do for SCIC before I hand over control to CPU2 or can I configure it on CPU2 after hand-over?  As it stands now my initialization registers and pin MUX and GMUX are all set after the PCLKCR regs.

    MUX and GMUX I have set up for SCIC for reference

    EALLOW;

    GpioCtrlRegs.GPEMUX1.bit.GPIO139 = 2;
    GpioCtrlRegs.GPEMUX1.bit.GPIO140 = 2;
    GpioCtrlRegs.GPEGMUX1.bit.GPIO139 = 1;
    GpioCtrlRegs.GPEGMUX1.bit.GPIO140 = 1;

    EDIS;