TMS320F28377S: Where is hardware detected "counter = 0"?

Sh.Sasaki

Part Number: TMS320F28377S

Hi Vasudha-san,

I ask additional questions about the following threads:

https://e2e.ti.com/support/microcontrollers/c2000/f/171/p/812087/3024935#3024935

Vasudha Bhadoria said:

We discussed over this and concluded that making TBCTR = 0 or TBCTR = PRD through software can lead to inconsistent behaviour.
When the interrupt gets generated. counter is incrementing and when we write TBCTR = 0 or PRD in ISR this leads to counter load with specific value. Since the increment and load are not synchronized with TBCLK much slower than SYSCLK, this leads to inconsistent behaviour wherein counter = 0 is not getting detected by hardware.

Where is hardware detected "counter = 0"?

Is it a falling edge from PRD to "0"?

over 6 years ago

0 Vasudha Bhadoria over 6 years ago

TI__Genius 10845 points

Hi,

I think it should be after TBCTR = 0 and not at the falling edge as per TRM description. I will check this with design team and get back.

Thanks

Vasudha

0 Sh.Sasaki over 6 years ago in reply to Vasudha Bhadoria

Guru 13625 points

Hi Vasudha-san,

Thank you for your support.

I'm looking forward to hearing from you.

0 Vasudha Bhadoria over 6 years ago in reply to Sh.Sasaki

TI__Genius 10845 points

Hi,

I checked the above scenario, cnt = 0 signal is generated on next epwmclk after the TBCTR value becomes zero.

I am closing this thread ans would be using the other opened thread for rest of the queries. Please use below single thread for all the communication related to this issue.

https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/821170

Thanks

Vasudha

C2000™︎ microcontrollers

C2000 microcontrollers forum

TMS320F28377S: Where is hardware detected "counter = 0"?