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TMS320F28021: Questions about ADC sampling process

Rayna Wang
Expert 3680 points

Part Number: TMS320F28021

Hi Team,

I have some questions about the behavior of Ch capacitor during for example SOC0 to SOC1 conversion process.

1. The switch is closed during S/H window, and the Ch will be charged by Cp and Cs capacitors. My question is that what's the behavior from the end of S0C0 S/H window to the beginning of SOC1 S/H window. Will Ch discharges completely, why or why not? How to make sure the next sampling is correct?

2. Is F2802x ADC sampling process same with F28004x and F2837xd(12-bit mode), and could we refer their computational formulas for F2802x to calculate the S+H duration?

Thanks!

-Rayna

  • 0
    TI__Guru 62975 points

    Rayna Wang said:
    1. The switch is closed during S/H window, and the Ch will be charged by Cp and Cs capacitors. My question is that what's the behavior from the end of S0C0 S/H window to the beginning of SOC1 S/H window. Will Ch discharges completely, why or why not? How to make sure the next sampling is correct?

    This note was added to the TRM to clarify that the Ch capacitor retains its residual charge between conversions.  There is no charging or discharging.

    The reason for this is that a properly matched ACQPS window will not require any preconditioning of the Ch capacitor, and the addition of Ch preconditioning circuitry will add complexity and introduce another point of failure.

    Rayna Wang said:
    2. Is F2802x ADC sampling process same with F28004x and F2837xd(12-bit mode), and could we refer their computational formulas for F2802x to calculate the S+H duration?

    Yes, the formulas from F28004x and F2837x are generic and would apply to the F2802x ADC as well.

  • 0 in reply to tlee
    TI__Expert 3680 points

    Hi tlee,

    Thanks!

    Does that mean the following steps, during the ADC conversions, 

    1. When in SOC0 S/H window, the switch is closed, then Cp & Cs charge or discharge Ch capacitor, which depending the source level. Finally, the Ch voltage value which at the end of S/H window will be stored in ADCResult register.

    2. Between conversions, the switch is opened, the Ch retains its residual charge.

    Hope you could correct me, if any mistake.

    Thanks!/Rayna

  • 0 in reply to Rayna Wang
    TI__Guru 62975 points

    Rayna,

    Yes, you are correct.  If Cs is small, then Ch is charged primarily by the source signal itself.

    -Tommy

  • 0 in reply to tlee
    TI__Expert 3680 points

    Hi Tommy,

    Thanks for your clarification.

    However, there are still some questions about A & B channels, customer confused.

    1. For example, if set AdcRegs.SOCPRICTL.bit.SOCPRIORITY = 8, just using sequence SOC7-> S0C8->SOC9, reflected to ADC pin sequence is A1->B1->B2.

    Condition: when B1 is in S/H sampling window, at this moment A1 is triggered, and after a while B2 is triggered, so the sampling sequence is B1->A1->B2.

    Questions: what the behavior of Ch capacitance of B channels, when B1 in conversion time while A1 in S/H window, is B converter switch open or closed and will the Ch discharge after B1 finish conversion?

    2. If the sampling pins changed from A channels to B channels, are there some requirements for A/B channels, for example, if A channel need to be low impedance, while B need to be high impedance, or not?

    -Rayna

  • 0 in reply to Rayna Wang
    TI__Guru 62975 points

    Rayna Wang said:
    1. For example, if set AdcRegs.SOCPRICTL.bit.SOCPRIORITY = 8, just using sequence SOC7-> S0C8->SOC9, reflected to ADC pin sequence is A1->B1->B2.

    Condition: when B1 is in S/H sampling window, at this moment A1 is triggered, and after a while B2 is triggered, so the sampling sequence is B1->A1->B2.

    Questions: what the behavior of Ch capacitance of B channels, when B1 in conversion time while A1 in S/H window, is B converter switch open or closed and will the Ch discharge after B1 finish conversion?

    A side effect of supporting the simultaneous sampling mode is that the Ch switches are open and closed at the same time for both the A and B channels, even when operating in sequential sampling mode. While A1 is sampling, B1 will also be sampled, but the ADC will not convert B1 in sequential sampling mode for SOC7.

    Rayna Wang said:
    2. If the sampling pins changed from A channels to B channels, are there some requirements for A/B channels, for example, if A channel need to be low impedance, while B need to be high impedance, or not?

    I am not sure that I understand this question. There are no requirements for channels that are not converted.

  • 0 in reply to tlee
    TI__Expert 3680 points

    Hi Tommy,

    In question 2, supposed that the A/B channels all used in ADC sampling circuit, what's the requirement configuration for this two kinds of pins? 

    Thanks!

    -Rayna

  • 0 in reply to Rayna Wang
    TI__Guru 62975 points

    Rayna,

    The simultaneous sampling mode does not have any additional requirements over sequential sampling. Everything should work the same as long as the signal conditioning matches the configured ACQPS window.

    Are you trying to debug a specific problem?

    -Tommy

  • 0 in reply to tlee
    Prodigy 190 points

    Hi Tommy:

         I am the user for this questions,I uploaded a word to help you see which of the two situations is right,left or right?Adc优先等级采样顺序梳理.docx

  • 0 in reply to user1745435
    TI__Guru 62975 points

    user1745435,

    Generally, your right-side scenario applies.  For sequential sampling, the ADC state machine will not separate the S/H and Conversion stages.

    However, for simultaneous sampling, the ADC state machine will separate the B-channel S/H from the Conversion in order to sample the A and B channels at the same time:

    The above simultaneous sampling behavior will carry over to sequential sampling as a non-functional side effect like this:

    The order of SOC processing when multiple triggers are received is determined by the SOC priority settings as described in the TRM.

    -Tommy

  • 0 in reply to tlee
    Prodigy 190 points

    Hi,Tommy:

            I forgot to remind you that sequential sampling is the current mode.

           Question 1: The second figure is not very clear. What sampling sequence and configuration is it? Can you describe it in detail?

           Question 2: If this Ch capacitor is charged very high by INA with high priority level in the second case of figure on the right side of word provided by me, does it mean that the input voltage of INB with low priority level in the next channel is lower than that of Ch, and Ch will form discharge operation to ensure that the sampling voltage is the input voltage?

         

  • 0 in reply to user1745435
    Prodigy 190 points

    Hi,Tommy:

             If the second problem exists, is there a good solution??

  • 0 in reply to user1745435
    TI__Guru 62975 points

    user1745435 said:
    Question 1: The second figure is not very clear. What sampling sequence and configuration is it? Can you describe it in detail?

    The second scenario that I attached was with Sequential Sampling and Overlap modes where the ADC_A0 trigger is received before the ADC_B0 trigger. 

    When a sequential sampling trigger is received, the triggered channel and its paired simultaneous channel will both close their S/H switches simultaneously.  So if only A0 receives a trigger, the Ch for both A0 and B0 will charge at the same time.  The A0 Ch is converted, but the B0 Ch is not converted because it is not triggered.

    If B0 is triggered while the A0 SOC is active, the B0 Ch will sample again just prior to B0 conversion.  This is what is shown in the example.

    user1745435 said:
    Question 2: If this Ch capacitor is charged very high by INA with high priority level in the second case of figure on the right side of word provided by me, does it mean that the input voltage of INB with low priority level in the next channel is lower than that of Ch, and Ch will form discharge operation to ensure that the sampling voltage is the input voltage?

    I think the short answer is yes.  The Ch capacitor is not biased or conditioned between ADC conversions so there will be carryover charge from the previous conversion.  The ADC was designed with the assumption that the input signal will be properly conditioned such that it can charge (or discharge) the Ch capacitor within acceptable accuracy levels within the configured ACQPS window.

    For high bandwidth sampling, a fast buffer can be used to rapidly settle the Ch voltage.  For low bandwidth sampling, a large capacitor can be placed on the ADC input pin for charge sharing.  The ACQPS setting can be adjusted to accommodate different signal characteristics.

  • 0 in reply to tlee
    Prodigy 190 points

    Hi,tlee:

             thank you for your replay~~