Hi
when DSP28035 EPWM1SYNCO set to disable and EPWM4's TBCTL[CTRMODE] set to enable, what EPWM4SYNCI state is? 0?1?
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Hi
when DSP28035 EPWM1SYNCO set to disable and EPWM4's TBCTL[CTRMODE] set to enable, what EPWM4SYNCI state is? 0?1?
Hi,
Please refer to the Figure 3-7. Time-Base Counter Synchronization Scheme 1
of the device TRM http://www.ti.com/lit/ug/sprui10/sprui10.pdf
In this case the sync input for EPWM4 (EPWM4SYNCI) will be determined by the syncout configuration set in EPWM3.
If it's set to disable (i.e. EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;) - then the EPWM4SYNCI would be low and no sync action will happen inside EPWM4.
Thank you for your reply。
DSP28035 EPWM1SYNCI Input square wave signal. When the high-level time of the square wave signal is less than 3.8us, EPWM1SYNCO will output a Pulse on the rising edge; when the high-level time of the square wave signal is greater than 3.8us, the Pulse signal will lag; if the square wave signal is high Continue to increase, will generate multiple Pulse. why?
What is the width requirement of the EPWM1SYNCI input signal Pulse?
Thanks
Hi,
SYNCI timing requirements are specified in the data sheet (http://www.ti.com/lit/ds/symlink/tms320f28035.pdf).
Refer to Table 6-50. ePWM Timing Requirements
If you are not using any GPIO filter/qualification on the SYNCI input - it should be a minimum of 2 System Clock cycles.
user1388828 said:square wave signal is greater than 3.8us, the Pulse signal will lag; if the square wave signal is high Continue to increase, will generate multiple Pulse
Hi,
Were you able to resolve this issue? If not, can you share the details requested above?