Tool/software: Code Composer Studio
I have used the following code. Earlier it was run good in CCSV8. I have modified the ADC_SOC example with my code. Code is building but It is pausing at invalid ISR function in Defaultsr.C file.After resuming interrupt ISRs are not using. I am attaching my code below please sugget any corrections I need to do.
//########################################################################### // // FILE: Example_2833xAdcSoc.c // // TITLE: ADC Start of Conversion Example // //! \addtogroup f2833x_example_list //! <h1> ADC Start of Conversion (adc_soc)</h1> //! //! This ADC example uses ePWM1 to generate a periodic ADC SOC on SEQ1. //! Two channels are converted, ADCINA3 and ADCINA2. //! //! \b Watch \b Variables \n //! - Voltage1[10] - Last 10 ADCRESULT0 values //! - Voltage2[10] - Last 10 ADCRESULT1 values //! - ConversionCount - Current result number 0-9 //! - LoopCount - Idle loop counter // //########################################################################### // $TI Release: F2833x Support Library v2.00.00.00 $ // $Release Date: Tue Jun 26 03:14:14 CDT 2018 $ // $Copyright: // Copyright (C) 2009-2018 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### // // Included Files // #include "DSP28x_Project.h" // Device Headerfile and Examples Include File #include <IQmathLib.h> #include <math.h> // // Function Prototypes // __interrupt void adc_isr(void); __interrupt void cpu_timer0_isr(void); void InitEPwm1Example(void); void Gpio_setup1(void); Uint16 LoopCount,iwstatus=0,ipstatus=0; Uint16 ConversionCount,state=0,scount=0; // // Main // void main(void) { // // Step 1. Initialize System Control: // PLL, WatchDog, enable Peripheral Clocks // This example function is found in the DSP2833x_SysCtrl.c file. // InitSysCtrl(); EALLOW; #if (CPU_FRQ_150MHZ) // Default - 150 MHz SYSCLKOUT // // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3) = 25.0 MHz // #define ADC_MODCLK 0x3 #endif #if (CPU_FRQ_100MHZ) // // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2) = 25.0 MHz // #define ADC_MODCLK 0x2 #endif EDIS; // // Define ADCCLK clock frequency ( less than or equal to 25 MHz ) // Assuming InitSysCtrl() has set SYSCLKOUT to 150 MHz // EALLOW; SysCtrlRegs.HISPCP.all = ADC_MODCLK; EDIS; // // Step 2. Initialize GPIO: // This example function is found in the DSP2833x_Gpio.c file and // illustrates how to set the GPIO to it's default state. // // InitGpio(); // Skipped for this example // // Step 3. Clear all interrupts and initialize PIE vector table: // Disable CPU interrupts // DINT; // // Initialize the PIE control registers to their default state. // The default state is all PIE interrupts disabled and flags // are cleared. // This function is found in the DSP2833x_PieCtrl.c file. // InitPieCtrl(); // // Disable CPU interrupts and clear all CPU interrupt flags: // IER = 0x0000; IFR = 0x0000; // // Initialize the PIE vector table with pointers to the shell Interrupt // Service Routines (ISR). // This will populate the entire table, even if the interrupt // is not used in this example. This is useful for debug purposes. // The shell ISR routines are found in DSP2833x_DefaultIsr.c. // This function is found in DSP2833x_PieVect.c. // InitPieVectTable(); // // Interrupts that are used in this example are re-mapped to // ISR functions found within this file. // EALLOW; // This is needed to write to EALLOW protected register PieVectTable.ADCINT = &adc_isr; PieVectTable.TINT0 = &cpu_timer0_isr; EDIS; // This is needed to disable write to EALLOW protected registers InitCpuTimers(); // For this example, only initialize the Cpu Timers #if (CPU_FRQ_150MHZ) // // Configure CPU-Timer 0 to interrupt every 500 milliseconds: // 150MHz CPU Freq, 50 millisecond Period (in uSeconds) // ConfigCpuTimer(&CpuTimer0, 150, 50); #endif #if (CPU_FRQ_100MHZ) // // Configure CPU-Timer 0 to interrupt every 500 milliseconds: // 100MHz CPU Freq, 50 millisecond Period (in uSeconds) // ConfigCpuTimer(&CpuTimer0, 100, 500000); #endif CpuTimer0Regs.TCR.all = 0x4000; // // Step 4. Initialize all the Device Peripherals: // This function is found in DSP2833x_InitPeripherals.c // // InitPeripherals(); // Not required for this example InitAdc(); // For this example, init the ADC Gpio_setup1(); InitEPwm1Example(); // // Step 5. User specific code, enable interrupts: // // Enable ADCINT in PIE // PieCtrlRegs.PIEIER1.bit.INTx6 = 1; PieCtrlRegs.PIEIER1.bit.INTx7 = 1; IER |= M_INT1; // Enable CPU Interrupt 1 EINT; // Enable Global interrupt INTM ERTM; // Enable Global realtime interrupt DBGM LoopCount = 0; ConversionCount = 0; // // Configure ADC // AdcRegs.ADCTRL3.bit.SMODE_SEL=0; AdcRegs.ADCMAXCONV.all = 0x0000; // Setup 4 conv's on SEQ1 AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x8; // Setup ADCINA7 - Ipv read. // // Enable SOCA from ePWM to start SEQ1 // AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1; AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1; // Enable SEQ1 interrupt (every EOS) for(;;) { LoopCount++; } } // // adc_isr - // __interrupt void adc_isr(void) { Ipv[count]=(AdcRegs.ADCRESULT0 >>4); //5 ipv AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; // Reset SEQ1 AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; // Clear INT SEQ1 bit PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE return; } __interrupt void cpu_timer0_isr(void) { CpuTimer0.InterruptCount++; // // Acknowledge this interrupt to receive more interrupts from group 1 // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; } void Gpio_setup1(void){ EALLOW; GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0; // Enable pullup on GPIO0 GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pullup on GPIO1 GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // GPIO0 = PWM1A GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // GPIO1 = PWM1B EDIS; } void InitEPwm1Example(void) { // // Setup TBCLK // //EPWM1 A and B are GPIO 0 and 1 EPwm1Regs.TBCTL.bit.CTRMODE = 0; // Count up down EPwm1Regs.TBPRD = 3750; // Set timer period EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 EPwm1Regs.TBCTR = 0x0000; // Clear counter EPwm1Regs.TBCTL.bit.HSPCLKDIV = 001; // Clock ratio to SYSCLKOUT EPwm1Regs.TBCTL.bit.CLKDIV = 000; EPwm1Regs.TBCTL.bit.SYNCOSEL=1; EPwm1Regs.CMPA.half.CMPA =1875; // Set compare A value EPwm1Regs.CMPB = 1875; // Set Compare B value EPwm1Regs.DBCTL.bit.OUT_MODE=3; EPwm1Regs.DBCTL.bit.POLSEL=2; EPwm1Regs.DBCTL.bit.IN_MODE=0; EPwm1Regs.DBRED=50; EPwm1Regs.DBFED=50; EPwm1Regs.AQCTLA.bit.CAU=2; // Set PWM1A on Zero EPwm1Regs.AQCTLA.bit.PRD=1; EPwm1Regs.AQCTLB.bit.CBU=2; EPwm1Regs.AQCTLB.bit.PRD=1; EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC from from CPMA on upcount EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event } // // End of File //
