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TMS320F28388S: CM <-> Communication

evs
Genius 5910 points
Part Number: TMS320F28388S
Other Parts Discussed in Thread: TMDSCNCD28388D

I read the datasheet with interest. Only I don't understand how TI solved the following:

With high speed communication comes a lot of data. How to manage?

 The CM has a 64kbyte data buffer. That is substantiation but not a lot. I checked the Emif the CM is not connected to it. So it is not possible to increase the data size for storing communication data.

 So the data needs to be managed on the fly. That is the lot, with a 100(?1000?)Mbit connection.

I have some questions:

- Is it possible to send interrupts from the CM->CPU1 and CPU1>CM?

- Is it possible to do a CM.DMA -> CPU.DMA transfer

- Other option is a fifo but 2kbyte shared data not a lot. So that can generate a lot of overhead especially when the data needs to be on polling bases

- What is TI suggested solution to controlling high speed communication data?

- What is the planning for releasing the TMS320F2838x series? When Can i order the TMDSCNCD28388D at farnell or mouser?

Thanks!

  • 0
    TI__Guru** 115881 points

    Hi,

    Thank you for your interest in this device. I'll share your feedback with our architecture team.

    On your specific queries -

    - Is it possible to send interrupts from the CM->CPU1 and CPU1>CM?

    Yes, there are multiple IPC (inter processor communication) interrupts.

    - Is it possible to do a CM.DMA -> CPU.DMA transfer

    It can be done via IPC MSG RAMs which are accessible by CPU1->DMA and CM-uDMA.

    - Other option is a fifo but 2kbyte shared data not a lot. So that can generate a lot of overhead especially when the data needs to be on polling bases

    As mentioned earlier, interrupt and DMA access to IPC MSG RAMs are available

    - What is TI suggested solution to controlling high speed communication data?

    CPU1 has access to some of the high speed communication IPs like USB and EtherCAT to allow partition of tasks between CPU1/CM.

    - What is the planning for releasing the TMS320F2838x series? When Can i order the TMDSCNCD28388D at farnell or mouser?

    You should be able to order the sample now. Production parts will be available in 2Q 2020.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Genius 5910 points

    Vivek,

    Thanks for the detailed reply. That answers a lot of my questions. Only I don't understand how CPU1 and CM can have control over 1 peripheral.

    Vivek Singh said:
    CPU1 has access to some of the high speed communication IPs like USB and EtherCAT to allow partition of tasks between CPU1/CM.

    Have you some more info how this is intended?

    Thanks.

    size note:

    Didn't make a lot more sense when the EMIF was directly connected to the CM. And CPU1 and CPU2 are assigned memory space via the CM.MPU

     

  • 0 in reply to evs
    TI__Guru** 115881 points

    Hi,

    Thanks for the detailed reply. That answers a lot of my questions. Only I don't understand how CPU1 and CM can have control over 1 peripheral.

    CPU1 and CM can not have control over 1 peripheral at same time. There are peripherals like USB/EtherCAT/DCAN which can be assigned to CPU1 or CM. Based on memory requirement, user can assign them to CPU1 instead of CM.

    Regards,

    Vivek Singh