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TMS320F28035 I2C module: STP bit question

Adrian Dudau
Prodigy 20 points

Hi,

I was wondering under what circumstances does the hardware (I2C module) write a 1 to the STP bit of the I2CMDR register?

I have the following scenario: While transferring data (reading with stop) on the I2C bus, i get a timeout and i want to reset the I2C module and clear it to start another operation. The only problem is that even if I explicitly write a 0 in the I2caRegs.I2CMDR.bit.STP bit, it is set to 1 by the hardware after some time. What causes this behaviour, and how can i clear the STP bit to prepare for the next operation? What happens if my next transfer needs to be of a NO STOP type (STP must be configured to 0)?

--Adrian

 

 

  • 0
    TI__Mastermind 20850 points

    Hi Adrian,

    If you are using the I2C in Master Receiver mode it will issue a STOP after it receives exactly I2CCNT number of bytes from the slave device. In the event of a timeout you could reset the I2C to clear the STP bit (clear then set IRS in the mode register).

    You can use the repeated start condition to continuously transfer data without stopping. Dont set the STP bit when you begin your transfer. One the master receives I2CCNT number of bits you can issue a new Start condition (STT) to start the transfer all over again.

  • 0 in reply to Vishal_Coelho
    Prodigy 20 points

    Hi Vishal,

     

    Thank you for your reply. However, my problem is that, when i get a timeout, even if i do a reset, the STP bit is cleared for the moment, but after some time it is automatically set back to 1 by the hardware, without me starting any new transfers.

  • 0 in reply to Adrian Dudau
    TI__Mastermind 20850 points

    Adrian, could you post your code or possible the I2C part. I can try and debug on the boards I have.