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TMS320F28377D: TZflag Async set when Multi ePWW using the same Tz source(GPIO)

DongFeng
Intellectual 330 points

Part Number: TMS320F28377D
Other Parts Discussed in Thread: C2000WARE

Hi,

I am using ePWM1A~4A for a power converter(full bridge).

TZ1 derived from hardware OCP through GPIO is used for all the 4 ePWM units while only ePWM1 TZINT(interrupt) is enabled. --------> BTW, I think this is just a common usage.

Gpio for TZ1 is configured as Async and using No-filter.

What confused me is that not all the ePWM units are triggered at the same time. Not all OST bit(EPWMxRegs.TZFLAG.bit.OST) is set and latched all the time, so not all the PWM is shut down at the same time.

Will this just happen under some extremely unusual situation or because something is wrong in my configuration?

Thanks. 

 

  • 0
    TI__Expert 5430 points

    Hi DongFeng,

    It is common to trip multiple PWMs simultaneously upon a single trip source (TZ1 in your case). So I suspect something missing in your configuration.

    Please check if you have configured the tripzone related registers(particularly the TZSEL, TZCTL registers) for each of the PWM instances correctly. You can refer to the example in the C2000Ware about the epwm_tripzone. Although the example configures only one PWM to trip, it can be extended to other PWM instances as well.

    Thanks & Regards

    Pramod

  • 0 in reply to Pramod P
    Intellectual 330 points

    Hi，Pramod：

    Thanks for your support.

    I am confident that the basic configuration would not be wrong that way.  And the epwm unit is not the same one when problem occurs.

    When I chang it to SYNC mode for the GPIO,  the problem is gone.  I add 3 samples filter further to avoid unexpected trigger.

    I am still not clear the reason. Any comments?

    Thanks.

  • 0
    TI__Genius 10845 points

    Hi, 

    Can you provide more details on this? How much variation are you seeing among the EPWM instances.

    Also, are these pwms synchronised? If yes, details on phase difference between PWMs.

    Thanks

    Vasudha

  • 0 in reply to Vasudha Bhadoria
    Intellectual 330 points

    Hi,Vasudha

    Thanks for your concern.

    I don't keep repeating the problem frequently when I found it is not with specific ePWM unit. If I have to make a conclusion, it seems that ePWM2 has more chance in my application.

    EPWM1~8 are used and synchronized in my application(2 full bridges). No phase shift exists in the counter.  Different DB usd to produce a little phase shift which is needed in my application.

    Phase shift registers equal to 2 for epwm2~8.

    And the trigger input is actually some unexpected noise.  

    In my understanding,  the glitch on TZ causes some internal misjudgment on 200M device though I don't know what it is.

    Thanks

  • 0 in reply to DongFeng
    TI__Expert 5430 points

    Hi DongFeng,

    Please refer to the below explanation from the TRM regarding the pulse width of the input TZ signal and also the GPIO(Section 15.9.2 Operational highlights of the Trip-Zone Submodule). This might be the cause for your problem.

    The trip-zone signals TZ1 to TZ6 (also collectively referred to as TZn) are active low input signals. When
    one of these signals goes low, or when a DCAEVT1/2 or DCBEVT1/2 force happens based on the
    TZDCSEL register event selection, it indicates that a trip event has occurred. Each ePWM module can be
    individually configured to ignore or use each of the trip-zone signals or DC events. Which trip-zone signals
    or DC events are used by a particular ePWM module is determined by the TZSEL register for that specific
    ePWM module. The trip-zone signals may or may not be synchronized to the ePWMclock (EPWMCLK)
    and digitally filtered within the GPIO MUX block. A minimum of 3*TBCLK low pulse width on TZn inputs is
    sufficient to trigger a fault condition on the ePWM module. If the pulse width is less than this, the trip
    condition may not be latched by CBC or OST latches. The asynchronous trip makes sure that if clocks are
    missing for any reason, the outputs can still be tripped by a valid event present on TZn inputs . The
    GPIOs or peripherals must be appropriately configured. For more information, see the device-specific
    version of the System Control and Interrupts chapter.

    Thanks & Regards

    Pramod

  • 0 in reply to Pramod P
    Intellectual 330 points

    Pramod,

    I agree with you.  

    As the same input used for different ePWM, it looks weird to me some units recognize the tz pulse (even latched) while others don't. There is no such detailed claim to this.

    Thanks