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TMS320F28335: How to achieve high precision phase shift with HRPWM for 28335?

Part Number: TMS320F28335

In the SPRUG02 document (TMS320x2833x, 2823x High Resolution Pulse Width Modulator), there is no example for the phase control mode for the HRPWM.

Now, I need use the HRPWM to achieve high precision of phase shift control. I configured the HRPWM relative registers refer to the duty control mode examples.

But high precision phase shifting was not achieved. I am doubt what is the problem?

 

EPwm1 Registers configuration:

    EPwm1Regs.TBPRD = EPWM_TIMER_TBPRD;           // Set timer period 801 TBCLKs
    EPwm1Regs.TBPHS.half.TBPHS = 0;                             // Phase is 0
    EPwm1Regs.TBCTR = 0x0000;                                        // Clear counter

    EPwm1Regs.CMPA.half.CMPA = (EPWM_TIMER_TBPRD>>1); 
    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
    EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE;
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;         
    EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
    EPwm1Regs.TBCTL.bit.PHSDIR = TB_UP;              
    EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;


    EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;   

    EPwm1Regs.AQCTLA.bit.ZRO = AQ_CLEAR;
    EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;

    EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm1Regs.DBRED = DeadBand;
    EPwm1Regs.DBFED = DeadBand;

EPwm4 Registers configuration:

    EPwm4Regs.TBPRD = EPWM_TIMER_TBPRD;
    EPwm4Regs.TBPHS.half.TBPHS = (EPWM_TIMER_TBPRD>>1);
    EPwm4Regs.TBPHS.half.TBPHSHR = (1<<8);       
    EPwm4Regs.TBCTR = 0x0000;

    EPwm4Regs.CMPA.half.CMPA = (EPWM_TIMER_TBPRD>>1);
    EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
    EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE;
    EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
    EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;
    EPwm4Regs.TBCTL.bit.PHSDIR = TB_UP;
    EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;

    EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;   

    EPwm4Regs.AQCTLA.bit.ZRO = AQ_SET;              // Set PWM1A on event A, up count
    EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR;            // Clear PWM1A on event A, down count

    EALLOW;
    EPwm4Regs.HRCNFG.all = 0x0;
    EPwm4Regs.HRCNFG.bit.EDGMODE = HR_BEP;
    EPwm4Regs.HRCNFG.bit.CTLMODE = HR_PHS;
    EPwm4Regs.HRCNFG.bit.HRLOAD  = HR_CTR_ZERO;
    EDIS;

    EPwm4Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    EPwm4Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm4Regs.DBRED = DeadBand;
    EPwm4Regs.DBFED = DeadBand;  

Phase shift control code:

    Width = 0.01 * (float)EPWM_TIMER_TBPRD;
    PhaseAng = (float)EPWM_TIMER_TBPRD * 0.5-Width;

    PHS_reg_val = (Uint16)PhaseAng;
    temp = (long)PhaseAng;
    temp = temp - ((long)PHS_reg_val<<15);
    PHSHR_reg_val = (temp*MEP_ScaleFactor[4])>>15;
    PHSHR_reg_val = PHSHR_reg_val << 8;
    PHSHR_reg_val += 0x0180;

    EPwm4Regs.TBPHS.all = ((long)PHS_reg_val)<<16 | PHSHR_reg_val;

Thanks for your attention and answers.