Hello,
I have a question on the nesting CPU interrupts for the DSP device of TMS320F28069M.
For maskable interrupts, is it feasible that a higher priority interrupt source can interrupt the interrupt servfice routine executed by a lower priority interrupt source?
This issue does not seem to be described explicitly in Chapter 3 (CPU Interrupts and Reset) of Literature Number SPRU430F (TMS320C28x CPU and Instruction Set Reference Guide).
If it is feasible, please inform me some relevant documents for this issue.
Thank you for your guidance.
With regards,
JS Yoo
