TMS320F280049: Timing specification for SPI

Shibata,

I don't have this information as of now. I need to check with design team and get back with you in a week.

Regards,

Manoj

Shibata,

Which SPI slave are you trying to talk to and how are you trying to talk to it?

Regards,

Manoj

Hi Manoj,

I will check with customer and get back to you.

Regards,

-Shibata

Hi Manoj,

Customer plan to connect EEPROM as a slave device.

They are also evaluating SPI example code in C2000Ware with LAUNCHXL-F280049C.

No problem found so far, but they would like to know the exact timing data for the SPISTE disable time that I mentioned earlier.

So that they can guarantee the productions to work.

Regards,

-Shibata

Shibata,

Is the customer using SPI FIFO?

Regards,

Manoj

Hi Manoj,

Manoj Santha Mohan said:

Is the customer using SPI FIFO?

I will check with customer, but could you please confirm the both cases, with/without FIFO?

Thanks & Regards,

-Shibata

Hi Manoj,

I confirmed with customer that they plan to use SPI FIFO.

If the time is different between the two cases (with/without FIFO), please provide the both.

Thanks,

-Shibata

Hi Manoj,

Any update on this?

Thanks & Regards,

-Shibata

Shibata,

In non-FIFO mode, when you send command one by one, the timing specification requested depends upon when the next command is executed from CPU. So, timing is depended upon how fast the CPU write to TX buffer and not SPI. That is the reason why this time is not spec'ed in DS.

In FIFO mode, when you send 2 (or) more commands you have the ability to chose FIFO depth. So, SPISTE will not be pulled high until it transmits all the data in FIFO.

Regards,

Manoj

Hi Manoj,

Thanks for your comment.

In non-FIFO mode, the SPISTE disable time depends on how fast the CPU write to TX buffer.

I agree with that at least for MAX value.

How about MIN value from SPI HW design point of view? (regardless of the CPU writing speed)

According to customer, the connected EEPROM requires 0.5 x SPICLK for the SPISTE disable time, and measured value is about 2.5 x SPICLK. So it looks good.

However, in case of connecting slower slave device to C2000, customer need to check if the MIN value is long enough for the slave.

That is why they wants to know the MIN value.

Could you please double check?

Thanks & Regards,

-Shibata

Shibata,

Min time is documented in DS. It is called "Delay time, SPICLK to SPISTE invalid".

If this is not what you are looking for, please specify the exact parameter name which you are looking for?

Regards,

Manoj

Hi Manoj,

The parameter “Delay time, SPICLK to SPISTE invalid” is not what I want to know.

Please see the diagram in my first post.

I want to know the MIN time between *1 and *2 shown by red allow.

It’s not documented in DS.

Regards,

-Shibata