TMS320F28069M: Problem while software force off

kishan pala

Part Number: TMS320F28069M
Other Parts Discussed in Thread: DRV8312, C2000WARE

Hello,

I am using driver IC UCC27201AQDDARQ1 with transistor to drive BLDC motor, I have changed the code BLDC_Censored which is for DRV8312 for the dead band, My problem is there is a slight overlap between ePWMA and ePWMB at the end, please let me know if there is some mistake in code. I am attaching code and waveforms here.

#define DEAD_BAND   10
#define OUT_MODE_ENABLE   3
#define IN_MODE_EPWMA 0

EPwm1Regs.DBCTL.bit.OUT_MODE = OUT_MODE_ENABLE;
EPwm2Regs.DBCTL.bit.OUT_MODE = OUT_MODE_ENABLE;
EPwm3Regs.DBCTL.bit.OUT_MODE = OUT_MODE_ENABLE;

EPwm1Regs.DBCTL.bit.POLSEL = 2;
EPwm2Regs.DBCTL.bit.POLSEL = 2;
EPwm3Regs.DBCTL.bit.POLSEL = 2;

EPwm1Regs.DBCTL.bit.IN_MODE = IN_MODE_EPWMA;
EPwm2Regs.DBCTL.bit.IN_MODE = IN_MODE_EPWMA;
EPwm3Regs.DBCTL.bit.IN_MODE = IN_MODE_EPWMA;

EPwm1Regs.DBRED = DEAD_BAND;
EPwm1Regs.DBFED = DEAD_BAND;
EPwm2Regs.DBRED = DEAD_BAND;
EPwm2Regs.DBFED = DEAD_BAND;
EPwm3Regs.DBRED = DEAD_BAND;
EPwm3Regs.DBFED = DEAD_BAND;

#define BLDCPWM_MACRO(v)                            /*                                                  */\
/* Convert "Period" (Q15) modulation function to Q0                                                     */\
    Tmp = (int32)v.PeriodMax*(int32)v.MfuncPeriod;  /* Q15 = Q0xQ15                                     */\
    Period = (int16)(Tmp>>15);                      /* Q15 -> Q0 (Period)                               */\
                                                    /*                                                  */\
/* Check PwmActive setting                                                                              */\
    if (v.PwmActive==1)                             /* PWM active high                                  */\
    {                                               /*                                                  */\
      GPR0_BLDC_PWM = 0x7FFF - v.DutyFunc;          /*                                                  */\
      CMPB_SMPL_POINT = 0x7FFF - (v.DutyFunc >> 1); /* Sample in center of PWM pulse using CMPB         */\
    }                                               /*                                                  */\
                                                    /*                                                  */\
    else if (v.PwmActive==0)                        /* PWM active low                                   */\
    {                                               /*                                                  */\
      GPR0_BLDC_PWM = v.DutyFunc;                   /*                                                  */\
      CMPB_SMPL_POINT = v.DutyFunc >> 1;            /* Sample in center of PWM pulse using CMPB         */\
    }                                               /*                                                  */\
                                                    /*                                                  */\
/* Convert "DutyFunc" or "GPR0_BLDC_PWM" (Q15) duty modulation function to Q0                           */\
    Tmp = (int32)Period*(int32)GPR0_BLDC_PWM;       /* Q15 = Q0xQ15                                     */\
    Tmp2 = (int32)Period*(int32)CMPB_SMPL_POINT;    /* Q15 = Q0xQ15                                     */\
    /*EPwm1Regs.CMPB = (int16)(Tmp2>>15);*/             /* Sample in center of PWM pulse using CMPB         */\
                                                    /*                                                  */\
/* State s1: current flows to motor windings from phase A->B, de-energized phase = C                    */\
    if (v.CmtnPointer==0)                           /*                                                  */\
    {                                               /*                                                  */\
      EPwm1Regs.AQCSFRC.bit.CSFB = 0;               /* Forcing disabled on output B of EPWM1            */\
      EPwm1Regs.AQCSFRC.bit.CSFA = 0;               /* Forcing disabled on output A of EPWM1            */\
      EPwm1Regs.AQCTLA.bit.CAU = 2;                 /* Set high when CTR = CMPA on UP-count             */\
      EPwm1Regs.AQCTLA.bit.ZRO = 1;                 /* Set low when CTR = Zero                          */\
      EPwm1Regs.AQCTLB.bit.CAU = 1;                 /* Set low when CTR = Zero                          */\
      EPwm1Regs.AQCTLB.bit.ZRO = 2;                 /* Set high when CTR = CMPA on UP-count             */\
      EPwm1Regs.CMPA.half.CMPA = (int16)(Tmp>>15);  /* PWM signal on output B of EPWM1 (Q15 -> Q0)      */\
      /*EPwm1Regs.AQCSFRC.bit.CSFA = 2;*/               /* Forcing a continuous High on output A of EPWM1   */\
                                                    /*                                                  */\
      EPwm2Regs.AQCSFRC.bit.CSFA = 1;               /* Forcing a continuous Low on output A of EPWM2    */\
      /*EPwm2Regs.AQCSFRC.bit.CSFB = 2;                Forcing a continuous High on output B of EPWM2   */\
                                                    /*                                                  */\
      EPwm3Regs.AQCSFRC.bit.CSFA = 1;               /* Forcing a continuous Low on output A of EPWM3    */\
      EPwm3Regs.AQCSFRC.bit.CSFB = 1;               /* Forcing a continuous Low on output B of EPWM3    */\
      EPwm1Regs.DBCTL.bit.OUT_MODE = 3;                                              \
      EPwm2Regs.DBCTL.bit.OUT_MODE = 3;                                              \
      EPwm3Regs.DBCTL.bit.OUT_MODE = 0;                                              \
       }                                               /*                                                  */\
                                                    /*                                                  */\
/* State s2: current flows to motor windings from phase A->C, de-energized phase = B                    */\
    else if (v.CmtnPointer==1)                      /*                                                  */\
    {                                               /*                                                  */\
      EPwm1Regs.AQCSFRC.bit.CSFB = 0;               /* Forcing disabled on output B of EPWM1           */\
      EPwm1Regs.AQCSFRC.bit.CSFA = 0;               /* Forcing disabled on output A of EPWM1            */\
      EPwm1Regs.AQCTLA.bit.CAU = 2;                 /* Set high when CTR = CMPA on UP-count             */\
      EPwm1Regs.AQCTLA.bit.ZRO = 1;                 /* Set low when CTR = Zero                          */\
      EPwm1Regs.AQCTLB.bit.CAU = 1;                 /* Set low when CTR = Zero                          */\
      EPwm1Regs.AQCTLB.bit.ZRO = 2;                 /* Set high when CTR = CMPA on UP-count             */\
      EPwm1Regs.CMPA.half.CMPA = (int16)(Tmp>>15);  /* PWM signal on output B of EPWM1 (Q15 -> Q0)      */\
      /*EPwm1Regs.AQCSFRC.bit.CSFA = 2;*/               /* Forcing a continuous High on output A of EPWM1   */\
                                                    /*                                                  */\
      EPwm2Regs.AQCSFRC.bit.CSFA = 1;               /* Forcing a continuous Low on output A of EPWM2    */\
      EPwm2Regs.AQCSFRC.bit.CSFB = 1;               /* Forcing a continuous Low on output B of EPWM2    */\
                                                    /*                                                  */\
      EPwm3Regs.AQCSFRC.bit.CSFA = 1;               /* Forcing a continuous Low on output A of EPWM3    */\
      /*EPwm3Regs.AQCSFRC.bit.CSFB = 2;                Forcing a continuous High on output B of EPWM3   */\
      EPwm1Regs.DBCTL.bit.OUT_MODE = 3;                                              \
      EPwm2Regs.DBCTL.bit.OUT_MODE = 0;                                              \
      EPwm3Regs.DBCTL.bit.OUT_MODE = 3;                                              \
    }                                               /*                                                  */\
                                                    /*                                                  */\
/* State s3: current flows to motor windings from phase B->C, de-energized phase = A                    */\
    else if (v.CmtnPointer==2)                      /*                                                  */\
    {                                               /*                                                  */\
      EPwm1Regs.AQCSFRC.bit.CSFA = 1;               /* Forcing a continuous Low on output A of EPWM1    */\
      EPwm1Regs.AQCSFRC.bit.CSFB = 1;               /* Forcing a continuous Low on output B of EPWM1    */\
                                                    /*                                                  */\
      EPwm2Regs.AQCSFRC.bit.CSFB = 0;               /* Forcing disabled on output B of EPWM2            */\
      EPwm2Regs.AQCSFRC.bit.CSFA = 0;               /* Forcing disabled on output A of EPWM2            */\
      EPwm2Regs.AQCTLA.bit.CAU = 2;                 /* Set high when CTR = CMPA on UP-count             */\
      EPwm2Regs.AQCTLA.bit.ZRO = 1;                 /* Set low when CTR = Zero                          */\
      EPwm2Regs.AQCTLB.bit.CAU = 1;                 /* Set low when CTR = Zero                          */\
      EPwm2Regs.AQCTLB.bit.ZRO = 2;                 /* Set high when CTR = CMPA on UP-count             */\
      EPwm2Regs.CMPA.half.CMPA = (int16)(Tmp>>15);  /* PWM signal on output B of EPWM2 (Q15 -> Q0)      */\
      /*EPwm2Regs.AQCSFRC.bit.CSFA = 2;*/               /* Forcing a continuous High on output A of EPWM2   */\
                                                    /*                                                  */\
      EPwm3Regs.AQCSFRC.bit.CSFA = 1;               /* Forcing a continuous Low on output A of EPWM3    */\
      /*EPwm3Regs.AQCSFRC.bit.CSFB = 2;                Forcing a continuous High on output B of EPWM3   */\
      EPwm1Regs.DBCTL.bit.OUT_MODE = 0;                                              \
      EPwm2Regs.DBCTL.bit.OUT_MODE = 3;                                              \
      EPwm3Regs.DBCTL.bit.OUT_MODE = 3;                                              \
    }                                               /*                                                  */\
                                                    /*                                                  */\
/* State s4: current flows to motor windings from phase B->A, de-energized phase = C                    */\
    else if (v.CmtnPointer==3)                      /*                                                  */\
    {                                               /*                                                  */\
      EPwm1Regs.AQCSFRC.bit.CSFA = 1;               /* Forcing a continuous Low on output A of EPWM1    */\
      /*EPwm1Regs.AQCSFRC.bit.CSFB = 2;                Forcing a continuous High on output B of EPWM1   */\
                                                    /*                                                  */\
      EPwm2Regs.AQCSFRC.bit.CSFB = 0;               /* Forcing disabled on output B of EPWM2            */\
      EPwm2Regs.AQCSFRC.bit.CSFA = 0;               /* Forcing disabled on output A of EPWM2            */\
      EPwm2Regs.AQCTLA.bit.CAU = 2;                 /* Set high when CTR = CMPA on UP-count             */\
      EPwm2Regs.AQCTLA.bit.ZRO = 1;                 /* Set low when CTR = Zero                          */\
      EPwm2Regs.AQCTLB.bit.CAU = 1;                 /* Set low when CTR = Zero                          */\
      EPwm2Regs.AQCTLB.bit.ZRO = 2;                 /* Set high when CTR = CMPA on UP-count             */\
      EPwm2Regs.CMPA.half.CMPA = (int16)(Tmp>>15);  /* PWM signal on output B of EPWM2 (Q15 -> Q0)      */\
      /*EPwm2Regs.AQCSFRC.bit.CSFA = 2;*/               /* Forcing a continuous High on output A of EPWM2   */\
                                                    /*                                                  */\
      EPwm3Regs.AQCSFRC.bit.CSFA = 1;               /* Forcing a continuous Low on output A of EPWM3    */\
      EPwm3Regs.AQCSFRC.bit.CSFB = 1;               /* Forcing a continuous Low on output B of EPWM3    */\
      EPwm1Regs.DBCTL.bit.OUT_MODE = 3;                                              \
      EPwm2Regs.DBCTL.bit.OUT_MODE = 3;                                              \
      EPwm3Regs.DBCTL.bit.OUT_MODE = 0;                                              \
    }                                               /*                                                  */\
                                                    /*                                                  */\
/* State s5: current flows to motor windings from phase C->A, de-energized phase = B                    */\
    else if (v.CmtnPointer==4)                      /*                                                  */\
    {                                               /*                                                  */\
      EPwm1Regs.AQCSFRC.bit.CSFA = 1;               /* Forcing a continuous Low on output A of EPWM1    */\
      /*EPwm1Regs.AQCSFRC.bit.CSFB = 2;                Forcing a continuous High on output B of EPWM1   */\
                                                    /*                                                  */\
      EPwm2Regs.AQCSFRC.bit.CSFA = 1;               /* Forcing a continuous Low on output A of EPWM2    */\
      EPwm2Regs.AQCSFRC.bit.CSFB = 1;               /* Forcing a continuous Low on output B of EPWM2    */\
                                                    /*                                                  */\
      EPwm3Regs.AQCSFRC.bit.CSFB = 0;               /* Forcing disabled on output B of EPWM3            */\
      EPwm3Regs.AQCSFRC.bit.CSFA = 0;               /* Forcing disabled on output A of EPWM3            */\
      EPwm3Regs.AQCTLA.bit.CAU = 2;                 /* Set high when CTR = CMPA on UP-count             */\
      EPwm3Regs.AQCTLA.bit.ZRO = 1;                 /* Set low when CTR = Zero                          */\
      EPwm3Regs.AQCTLB.bit.CAU = 1;                 /* Set low when CTR = Zero                          */\
      EPwm3Regs.AQCTLB.bit.ZRO = 2;                 /* Set high when CTR = CMPA on UP-count             */\
      EPwm3Regs.CMPA.half.CMPA = (int16)(Tmp>>15);  /* PWM signal on output B of EPWM3 (Q15 -> Q0)      */\
      /*EPwm3Regs.AQCSFRC.bit.CSFA = 2;*/               /* Forcing a continuous High on output A of EPWM3   */\
      EPwm1Regs.DBCTL.bit.OUT_MODE = 3;                                              \
      EPwm2Regs.DBCTL.bit.OUT_MODE = 0;                                              \
      EPwm3Regs.DBCTL.bit.OUT_MODE = 3;                                              \
    }                                               /*                                                  */\
                                                    /*                                                  */\
/* State s6: current flows to motor windings from phase C->B, de-energized phase = A                    */\
    else if (v.CmtnPointer==5)                      /*                                                  */\
    {                                               /*                                                  */\
      EPwm1Regs.AQCSFRC.bit.CSFA = 1;               /* Forcing a continuous Low on output A of EPWM1    */\
      EPwm1Regs.AQCSFRC.bit.CSFB = 1;               /* Forcing a continuous Low on output B of EPWM1    */\
                                                    /*                                                  */\
      EPwm2Regs.AQCSFRC.bit.CSFA = 1;               /* Forcing a continuous Low on output A of EPWM2    */\
      /*EPwm2Regs.AQCSFRC.bit.CSFB = 2;                Forcing a continuous High on output B of EPWM2   */\
                                                    /*                                                  */\
      EPwm3Regs.AQCSFRC.bit.CSFB = 0;               /* Forcing disabled on output B of EPWM3            */\
      EPwm3Regs.AQCSFRC.bit.CSFA = 0;               /* Forcing disabled on output A of EPWM3            */\
      EPwm3Regs.AQCTLA.bit.CAU = 2;                 /* Set high when CTR = CMPA on UP-count             */\
      EPwm3Regs.AQCTLA.bit.ZRO = 1;                 /* Set low when CTR = Zero                          */\
      EPwm3Regs.AQCTLB.bit.CAU = 1;                 /* Set low when CTR = Zero                          */\
      EPwm3Regs.AQCTLB.bit.ZRO = 2;                 /* Set high when CTR = CMPA on UP-count             */\
      EPwm3Regs.CMPA.half.CMPA = (int16)(Tmp>>15);  /* PWM signal on output B of EPWM3 (Q15 -> Q0)      */\
      /*EPwm3Regs.AQCSFRC.bit.CSFA = 2;*/               /* Forcing a continuous High on output A of EPWM3   */\
      EPwm1Regs.DBCTL.bit.OUT_MODE = 0;                                              \
      EPwm2Regs.DBCTL.bit.OUT_MODE = 3;                                              \
      EPwm3Regs.DBCTL.bit.OUT_MODE = 3;                                              \
    }

over 6 years ago

0 Cody Watkins over 6 years ago

TI__Mastermind 42195 points

Depending on the rise and fall time of your transistor you will need to adjust your dead band. Since you are still having some overlap increase this number until you get the desired effect. "#define DEAD_BAND 10"

Regards,
Cody

0 kishan pala over 6 years ago in reply to Cody Watkins

Intellectual 380 points

This is the output of DSP GPIO, in open condition.

0 Cody Watkins over 6 years ago in reply to kishan pala

TI__Mastermind 42195 points

OK, the concept still applies. You will need to increase your dead band so that you can avoid overlap while you signals are transitioning between VDDIO and VSS and vice versa.

Regards,
Cody

0 kishan pala over 6 years ago in reply to Cody Watkins

Intellectual 380 points

am I doing right configuration or is there a better way to do it? and if you notice waveform carefully then it is observed that the overlap occurs in last pulse only rest of the pulse have enough dead band, it works fine during AB and AC steps where there is PWM in A phase while we moved to BC step where we off PWM on A phase this problem occurs.

0 Cody Watkins over 6 years ago in reply to kishan pala

TI__Mastermind 42195 points

Your configuration looks fine. It is a little weird that one period overlaps more than the previous, but this shouldn't a configuration based issue unless you are modifying the configuration during run time.

Were you changing the width of the signal or something? Why is the last yellow pulse so much wider than the first?

Regards,
Cody

0 kishan pala over 6 years ago in reply to Cody Watkins

Intellectual 380 points

Yes I'm changing the width of the signal, but as of now it is constant. I have also checked with increasing the dead band but still problem persist.

If you observed carefully yellow pulse is not wider, it is looks wider because of two signals on top of pulse, I want you to implement this code in your system check the result.

0 Cody Watkins over 6 years ago in reply to kishan pala

TI__Mastermind 42195 points

Kishan,

it appears to me that the base of the second yellow pulse is slightly narrower than the other pulses.

What happened when you increased the dead band?

At this time I do not plan to run any experiments or implement this in code.'

Regards,
Cody

0 kishan pala over 6 years ago in reply to Cody Watkins

Intellectual 380 points

Same thing happens while increasing the dead band.

0 Cody Watkins over 6 years ago in reply to kishan pala

TI__Mastermind 42195 points

Could you provide a scope capture of the increased dead band?

Thanks,
Cody

0 kishan pala over 6 years ago in reply to Cody Watkins

Intellectual 380 points

0 Cody Watkins over 6 years ago in reply to kishan pala

TI__Mastermind 42195 points

Kishan,

I do not see anything glaringly wrong with your code. It is unclear to me why you want to remove the CSFx with CSFx and Dead Band output modifications. I do think that this method could work, but I do not see the advantage.

I do not have a good reason why your Dead Band delay is following a pattern, but I suspect that it has something to do with the way that you are switching the DB output mode. Unfortunately I do not have the resources to debug your entire code, however if you find a more specific issue like "when I set x the I see y, why does this occur?" then I will be able to help explain this or find a workaround.

If you want to see an example of the dead band working you can find that in C2000Ware here: C:\ti\c2000\C2000Ware_2_00_00_02\device_support\f2806x\examples\c28\epwm_deadband

Regards,
Cody

0 kishan pala over 6 years ago in reply to Cody Watkins

Intellectual 380 points

My problem is solved with the following changes:

EPwm1Regs.CMPCTL.bit.SHDWAMODE = 1;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = 1;

EPwm2Regs.CMPCTL.bit.SHDWAMODE = 1;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = 1;

EPwm3Regs.CMPCTL.bit.SHDWAMODE = 1;
EPwm3Regs.CMPCTL.bit.SHDWBMODE = 1;

EPwm1Regs.AQSFRC.bit.RLDCSF = 3;
EPwm2Regs.AQSFRC.bit.RLDCSF = 3;
EPwm3Regs.AQSFRC.bit.RLDCSF = 3;

As I have read in one of the post it may be because action qualifier was not taking place immediately and the dead band configuration is immediate.

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TMS320F28069M: Problem while software force off