TMS320F28377D: Simultaneous reads of the two IPC counter registers by separate CPUs during a counter wrap

This question is related to my previous question concerning the latching of IPCCOUNTERH when IPCCOUNTERL is being read by two processors.

What happens when CPU1 reads IPCCOUNTERH and CPU2 reads IPCCOUNTERL in the same clock cycle in the situation where IPCCOUNTERL has wrapped, and therefore IPCCOUNTERH increments?

1. CPU1 reads IPCCOUNTERL as 0xFFFFFFFF when {IPCCOUNTERH, IPCCOUNTERL} is {0xFFFFFFFF, 0xFFFFFFFF}. IPCCOUNTERH is latched as 0xFFFFFFFF.
2. IN THE NEXT CLOCK CYCLE
   1. CPU2 reads IPCCOUNTERL as 0x00000000 when {IPCCOUNTERH, IPCCOUNTERL} is {0x00000000, 0x00000000}. IPCCOUNTERH is latched as 0x00000000.
   2. AND CPU1 reads IPCCOUNTERH.

There is both a read (by CPU1) and an update (triggered by CPU2) of the IPCCOUNTERH register in the same clock cycle. What is the value of the read returned to CPU1? Is it the original latched value, the new latched value, or garbage?

Thanks in advance,

Iain