Part Number: LAUNCHXL-F28377S
Hello Everyone,
In the program which I wrote , I wanted that the compare sub-module in ePWM receives an external SIne wave which I supply to ADC pin so that I can get SINE PWM modulation. Actually I combined the 2 programs (ePWM_up and ADC_ePWM) which work fine when individually but combing them the PWM pulses are not generated.
Just want to know whether doing this is correct or not.....{ EPwm3Regs.CMPA.bit.CMPA = (unsigned int) AdcaResults;} because the sampled sine wave is stored in AdcaResults.
#include "F28x_Project.h"
void ConfigureADC(void);
void ConfigureEPWM(void);
void InitEPwm3Example(void);
void InitEPwm2Example(void);
void SetupADCEpwm(Uint16 channel); //unsigned Integer
interrupt void adca1_isr(void); //This function will be interrupted somewhere in the loop
#define RESULTS_BUFFER_SIZE 256 // 32-Bit
Uint16 AdcaResults[RESULTS_BUFFER_SIZE];
Uint16 resultsIndex;
volatile Uint16 bufferFull;
void main(void)
{
InitSysCtrl();
InitGpio();
CpuSysRegs.PCLKCR2.bit.EPWM3=1;
InitEPwm3Gpio();
InitEPwm2Gpio();
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
InitPieVectTable();
EALLOW;
PieVectTable.ADCA1_INT = &adca1_isr; //function for ADCA interrupt 1
EDIS;
EALLOW;
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 0;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =0;
EDIS;
InitEPwm3Example();
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =1;
EDIS;
ConfigureADC();
ConfigureEPWM();
SetupADCEpwm(0);
IER |= M_INT1; //Enable group 1 interrupts
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
for(resultsIndex = 0; resultsIndex < RESULTS_BUFFER_SIZE; resultsIndex++)
{
AdcaResults[resultsIndex] = 0; //To eradicate garbage value......
}
resultsIndex = 0;
bufferFull = 0;
PieCtrlRegs.PIEIER1.bit.INTx1 = 1;
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
do
{
EPwm1Regs.ETSEL.bit.SOCAEN = 1; //enable SOCA (ETSEL--Event Trigger to TRigger ADC)
EPwm1Regs.TBCTL.bit.CTRMODE = 0; //unfreeze, and enter up count mode
while(!bufferFull); //while bufferFull=1 dont run this loop
bufferFull = 0; //clear the buffer full flag
EPwm1Regs.ETSEL.bit.SOCAEN = 0; //disable SOCA
EPwm1Regs.TBCTL.bit.CTRMODE = 3; //freeze counter
asm(" ");
}while(1);
}
void ConfigureADC(void)
{
EALLOW;
AdcaRegs.ADCCTL2.bit.PRESCALE = 6; //set ADCCLK divider to /4
AdcSetMode(ADC_ADCA, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;
DELAY_US(1000);
EDIS;
}
//
// ConfigureEPWM - Configure EPWM SOC and compare values
//
void ConfigureEPWM(void)
{
EALLOW;
// Assumes ePWM clock is already enabled
EPwm1Regs.ETSEL.bit.SOCAEN = 0; // Disable SOC on A group
EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC on up-count
EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
EPwm1Regs.CMPA.bit.CMPA = 0x0800; // Set compare A value to 2048 counts
EPwm1Regs.TBPRD = 0x1000; // Set period to 4096 counts
EPwm1Regs.TBCTL.bit.CTRMODE = 3; // freeze counter
EDIS;
}
void SetupADCEpwm(Uint16 channel)
{
Uint16 acqps;
if(ADC_RESOLUTION_12BIT == AdcaRegs.ADCCTL2.bit.RESOLUTION)
{
acqps = 14; //75ns
}
else //resolution is 16-bit
{
acqps = 63; //320ns
}
EALLOW;
AdcaRegs.ADCSOC0CTL.bit.CHSEL = channel; //SOC0 will convert pin A0
AdcaRegs.ADCSOC0CTL.bit.ACQPS = acqps; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 5; //trigger on EPwm1 SOCA/C
AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 0; //end of SOC0 will set INT1 flag
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; //enable INT1 flag
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //make sure INT1 flag is cleared
EDIS;
}
interrupt void adca1_isr(void)
{
AdcaResults[resultsIndex++] = AdcaResultRegs.ADCRESULT0;
if(RESULTS_BUFFER_SIZE <= resultsIndex)
{
resultsIndex = 0;
bufferFull = 1;
}
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
if(1 == AdcaRegs.ADCINTOVF.bit.ADCINT1)
{
AdcaRegs.ADCINTOVFCLR.bit.ADCINT1 = 1; //clear INT1 overflow flag
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
}
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}
void InitEPwm3Example()
{
EPwm3Regs.TBPRD = 4000; // Set timer period
EPwm3Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm3Regs.TBCTR = 0x0000; // Clear counter
EPwm3Regs.CMPA.bit.CMPA = (unsigned int) AdcaResults;
//
// Setup TBCLK
//
EPwm3Regs.TBCTL.bit.SYNCOSEL = 01; // Sync output select
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count mode select
EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
//
// Set actions
//
EPwm3Regs.AQCTLA.bit.CAU = AQ_SET; // Action when CTR = CMPA on UP Count (EPWM-A)
// EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Action when CTR = CMPA on DOWN Count (EPWM-A)
// EPwm3Regs.AQCTLA.bit.PRD = AQ_SET; // Action when CTR = PRD (EPWM-A)
EPwm3Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // Action when CTR = ZRO (EPWM-A)
EPwm3Regs.AQCTLB.bit.CAU = AQ_SET; // Action when CTR = CMPA on UP Count (EPWM-B)
EPwm3Regs.AQCTLB.bit.CAD = AQ_CLEAR; // Action when CTR = CMPA on DOWN Count (EPWM-B)
// EPwm3Regs.AQCTLB.bit.PRD = AQ_SET; // Action when CTR = PRD (EPWM-B)
// EPwm3Regs.AQCTLB.bit.ZRO = AQ_CLEAR; // Action when CTR = ZRO (EPWM-B)
//
// Active Low PWMs - Setup Deadband
//
EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // Enable Deadband Out Mode
EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Deadband Polarity Select
EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL; // Enable Deadband IN Mode
EPwm3Regs.DBRED.bit.DBRED = 2*100; // Rising Edge Dead Band
EPwm3Regs.DBFED.bit.DBFED = 2*100; // Falling Edge Dead Band
}
//
// End of file
//
